RC28F256 Intel Corporation, RC28F256 Datasheet - Page 37

• Manufacturer Part Number: RC28F256
• Description: Intel StrataFlash Embedded Memory
• Manufacturer: Intel Corporation

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Table 17.
Datasheet
Clock Specifications
Synchronous Specifications
NOTES:
1.
2.
3.
4.
5.
6.
R101
R102
R103
R104
R105
R106
R108
R200
R201
R202
R203
R301
R302
R303
R304
R305
R306
R307
R312
Num
R111
R311
See
slew rate.
OE# may be delayed by up to t
Sampled, not 100% tested.
Address hold in synchronous burst mode is t
Applies only to subsequent synchronous reads.
See your local Intel representative for designs requiring higher than 40 MHz synchronous operation.
t
CHQV
Figure 13, “AC Input/Output Reference Waveform” on page 33
t
Symbol
FCLK/RCLK
t
t
t
t
t
t
t
AVCH/L
VLCH/L
ELCH/L
t
t
t
t
t
t
t
t
t
t
f
t
CH/CL
CHQX
CHAX
AVVH
ELVH
VLQV
VLVH
VHVL
VHAX
phvh
CHTV
CHVL
CHTX
APA
CLK
CLK
AC Read Specifications for 256/512-Mbit and 1-Gbit Densities (Sheet 2 of 2)
/ t
CLQV
Address setup to ADV# high
CE# low to ADV# high
ADV# low to output valid
ADV# pulse width low
ADV# pulse width high
Address hold from ADV# high
Page address access
RST# high to ADV# high
CLK frequency
CLK period
CLK high/low time
CLK fall/rise time
Address setup to CLK
ADV# low setup to CLK
CE# low setup to CLK
CLK to output valid
Output hold from CLK
Address hold from CLK
CLK to WAIT valid
CLK Valid to ADV# Setup
WAIT Hold from CLK
Intel StrataFlash
ELQV
Order Number: 306666, Revision: 001
Parameter
– t
GLQV
CHAX
after CE#’s falling edge without impact to t
®
or t
Embedded Memory (P30)
VHAX
Vcc = 1.8 V
Vcc = 1.7 V
, whichever timing specification is satisfied first.
Speed
for timing measurements and max allowable input
– 2.0 V
– 2.0 V
Min
10
10
10
10
30
25
10
9
5
9
9
9
3
3
3
-
-
-
-
-
-
-
ELQV
Max
.
85
88
25
40
20
20
3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1-Gbit P30 Family
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
April 2005
Notes
1,3,6
1,4,5
1,4
1,5
1,5
1,5
1
1
1
1
37