RC28F256 Intel Corporation, RC28F256 Datasheet - Page 54

• Manufacturer Part Number: RC28F256
• Description: Intel StrataFlash Embedded Memory
• Manufacturer: Intel Corporation

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1-Gbit P30 Family
10.3
Table 22.
April 2005
54
Read Configuration Register (RCR)
13:11
Mode
Read
RM
Bit
5:4
15
15
14
10
9
8
7
6
However, for a synchronous non-array read, the same word of data will be output on successive
clock edges until the burst length requirements are satisfied. Refer to the following waveforms for
more detailed information:
Read Configuration Register
The Read Configuration Register (RCR) is used to select the read mode (synchronous or
asynchronous), and it defines the synchronous burst characteristics of the device. To modify RCR
settings, use the Configure Read Configuration Register command (see
Commands” on page
RCR contents can be examined using the Read Device Identifier command, and then reading from
offset 0x05 (see
The RCR is shown in
Read Configuration Register Description (Sheet 1 of 2)
•
•
•
Read Mode (RM)
Reserved (R)
Latency Count (LC[2:0])
Wait Polarity (WP)
Data Hold (DH)
Wait Delay (WD)
Burst Sequence (BS)
Clock Edge (CE)
Reserved (R)
RES
14
R
Figure 19, “Synchronous Single-Word Array or Non-array Read Timing” on page 39
Figure 20, “Continuous Burst Read, showing an Output Delay Timing” on page 40
Figure 21, “Synchronous Burst-Mode Four-Word Read Timing” on page 41
13
Name
Latency Count
LC[2:0]
12
Section 14.2, “Read Device Identifier” on page
Intel StrataFlash
Order Number: 306666, Revision: 001
50).
Table
11
0 = Synchronous burst-mode read
1 = Asynchronous page-mode read (default)
Reserved bits should be cleared (0)
010 =Code 2
011 =Code 3
100 =Code 4
101 =Code 5
110 =Code 6
111 =Code 7 (default)
(Other bit settings are reserved)
0 =WAIT signal is active low
1 =WAIT signal is active high (default)
0 =Data held for a 1-clock data cycle
1 =Data held for a 2-clock data cycle (default)
0 =WAIT deasserted with valid data
1 =WAIT deasserted one data cycle before valid data (default)
0 =Reserved
1 =Linear (default)
0 = Falling edge
1 = Rising edge (default)
Reserved bits should be cleared (0)
Polarity
22. The following sections describe each RCR bit.
WAIT
WP
10
®
Data
Hold
DH
Embedded Memory (P30)
9
Delay
WAIT
WD
8
Burst
Seq
BS
7
Edge
CLK
CE
Description
6
RES
R
5
76).
RES
R
4
Section 9.2, “Device
Burst
Wrap
BW
3
2
Burst Length
BL[2:0]
Datasheet
1
0