CMX649 CML Microcircuits, CMX649 Datasheet
CMX649
Related parts for CMX649
CMX649 Summary of contents
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... High performance analog interfaces and sidetone include digital gain controls. Encoder and decoder voice activity detectors support powersaving. The CMX649 ADM Voice Codec supports 2.7V to 5.5V operation and is available in 20-pin SOIC (D3) and TSSOP packages (E3) packages. 2003 CML Microsystems Plc ...
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... ADM Coding Engine ................................................... 6 PCM Encoding and Decoding.................................... 7 Transcoding with the Encoder and Decoder ............ 8 Non-Linear Instantaneous Companding ................... 9 Digitally Controlled Amplifiers................................... 9 Microphone Amplifier................................................. 9 Programmable Anti-alias/image SC Filters ............... 9 Data Clock Recovery ................................................ 11 Data Scrambler/De-scrambler .................................. 11 Write Only Register Description .............................. 16 Read Only Register Description .............................. 35 2 CMX649 Page D/649/2 ...
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... Analog Output signal from decoder. Negative supply rail (Ground). Decoder voice activity detector output. Received signal serial data input. Decoder data clock. 4 – 16 MHz crystal oscillator input C-BUS control signals Clock signal for encoded data out. Encoded data output. CMX649 D/649/2 ...
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... A 4.096MHz Xtal/Clock input will yield exactly 16kbps/32kbps/64kbps internally generated data clock rates achieve good noise performance, V from extraneous in-band signals are very important recommended that the printed circuit board is laid out with a ground plane in the CMX649 area to provide a low impedance connection between the V pin and the V SS ...
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... General Description The CMX649 encodes and decodes analog audio signals to/from ADM, Linear PCM, µ-law PCM or A-law PCM. It has programmable clock dividers that enable it to use a range of 4-16 MHz crystal clocks and to sample the data over a large range of data rates. Programmable current sources for on-chip op-amps enable the overall power consumption to be optimised for any given supply voltage and clocking scheme, thus achieving extremely low working power levels ...
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... PCM IN PCM INPUT REG $E7 LINEAR PCM OUT Figure 5 PCM Encoding 7 PROGRAMMABLE ADM x STEP SIZE INPUT CONTROL REG $D8 ADM DELAY OUTPUT REGISTER REG $DA ADM INPUT REG $E8 ADM DELAY OUTPUT REGISTER REG $EA PROGRAMMABLE x STEP SIZE CONTROL CMX649 LINEAR PCM IN ADM IN ADM OUT D/649/2 ...
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... CONTROL REG $D8 ADM DELAY OUTPUT REGISTER REG $DA ADM INPUT REG $E8 ADM DELAY OUTPUT REGISTER REG $EA PROGRAMMABLE x STEP SIZE CONTROL PROGRAMMABLE ADM x STEP SIZE INPUT CONTROL REG $D8 ADM DELAY OUTPUT REGISTER REG $DA CMX649 LINEAR PCM IN ADM IN ADM OUT LINEAR PCM IN ADM IN D/649/2 ...
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... Typically, the audio filter bandwidth 2003 CML Microsystems Plc Side-tone audio is added to the audio output signal via 100k 10% R6 100k 10% 100 pF C6 20% C7 0.01 F 20% 9 VDD MIC OUT MIC - - + MIC + 20k BIAS 20k VSS 100k 10% 100k 10% 1.0 F 20% 1.0 F 20% CMX649 D/649/2 ...
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... Figure 10a Typical Anti-Alias/Image Filter Frequency Response 2003 CML Microsystems Plc th of the ADM bit rate (or lower) for “toll” (or better) quality audio 10,000 Frequency (Hz) 10 CMX649 th of the ADM bit ...
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... CML Microsystems Plc 1,000 10,000 Frequency (Hz the frequency of the output of the internal bit clock prescaler. 11 CMX649 ...
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... Time Constants $D0 & $E0 constant factor 2003 CML Microsystems Plc Polynomial coefficients in hex format 2 0x003 3 0x006 4 0x00C 5 0x014 6 0x030 7 0x060 8 0x08E 9 0x110 10 0x240 PCM | y | SIGNAL decay C 1/4 attack time 1/8 1/16 1/32 Figure 11 VAD Block Diagram 12 VAD LEVEL $D4 & $E4 VAD + OUT - 0.5 VAD Threshold $D2 & $E2 CMX649 D/649/2 ...
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... ADM Codec 5.2 C-BUS Description Address/Commands Instructions and data are transferred, via C-BUS, in accordance with the timing information given in Figure 12. Instruction and data transactions to and from the CMX649 consist of an Address/Command (A/C) byte followed by either: (i) (ii) Write Only C-BUS Registers HEX REGISTER ADDRESS/ ...
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... Time Constant 2 Order Integration Local Decoder Select ADM IN Output Select Select VAD Output Constant Source Companding Rule Integrator Order Estimator Zero location for nd Time Constant 2 Order Integration CMX649 BIT 0 (D0 Dec Zero Idle Channel Enhance ADM Output Select Dec Zero D/649/2 ...
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... Linear PCM Output Signal Bits Decode ADM Output Voice Activity Detector Level Output Bits Voice Activity Detector Level Output Bits BIT3 BIT 2 BIT 1 (D4) (D3) (D2) BIT3 BIT 2 BIT 1 (D4) (D3) (D2) Decode Processor Status CMX649 BIT 0 (D1) (D0) BIT 0 (D1) (D0) D/649/2 ...
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... Linear PCM Output Signal Bits Linear PCM Output Signal Bits Encode ADM Output Bit 6 Bit 5 Bit 4 -3dB Frequency BIT3 BIT 2 BIT 1 (D4) (D3) (D2) 2.9kHz 3.7kHz 5.0kHz 7.0kHz 10.0kHz 14.0kHz CMX649 BIT 0 (D1) (D0) D/649/2 ...
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... Steps Off -33.0dB -31.5dB -30.0dB -28.5dB -27.0dB -25.5dB -24.0dB -22.5dB -21.0dB -19.5dB -18.0dB -16.5dB -15.0dB -13.5dB -12.0dB -10.5dB -9.0dB -7.5dB -6.0dB -4.5dB -3.0dB -1.5dB 0.0dB 1.5dB 3.0dB 4.5dB 6.0dB 7.5dB 9.0dB 10.5dB 12.0dB CMX649 D/649/2 ...
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... CMX649 Off -7.5dB -7.0dB -6.5dB -6.0dB -5.5dB -5.0dB -4.5dB -4.0dB -3.5dB -3.0dB -2.5dB -2.0dB -1.5dB -1.0dB -0.5dB 0.0dB 0.5dB 1.0dB 1.5dB 2.0dB 2.5dB 3.0dB 3.5dB 4.0dB 4.5dB 5.0dB 5 ...
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... Normal operation (for bit rates greater than 64kbps). Power Level Setting Power down (Off). Lowest power (for bit rates less than 32kbps). Low power (for bit rates between 32kbps and 64kbps). Normal operation (for bit rates greater than 64kbps). 19 CMX649 D/649/2 ...
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... Normal operation (for audio bandwidths greater than 10kHz). Power Level Setting Power down (Off). Lowest power (for bit rates less than 32kbps). Low power (for bit rates between 32kbps and 64kbps). Normal operation (for bit rates greater than 64kbps). 20 CMX649 D/649/2 ...
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... ADM mode without buffered I ADM mode with buffered I Linear PCM with buffered I µ-law PCM with buffered I A-law PCM with buffered I B8X + B7X +B6X + B5X B4X + B3X + B2X + B1X CMX649 B0X D/649/2 ...
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... Bit 9 Bit 8 Divider Ratio Bit 7 Bit 6 Divider Ratio 2.000 8.000 15.500 15.750 16.000 22.000 31.250 46.750 CMX649 D/649/2 ...
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... Bit 3 Divider Ratio 0 0 1.000 0 1 2.000 1 0 2.250 1 1 2.625 0 0 3.000 0 1 3.125 1 0 3.375 1 1 3.500 Bit 1 Bit 0 Divider Ratio 0 0 1.000 0 1 2.000 1 0 2.250 1 1 2.625 0 0 3.000 0 1 3.125 1 0 3.375 1 1 3.500 23 CMX649 D/649/2 ...
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... Internally Generated encode clock Internally Generated from decode clock. Power Level Setting Power down (Off). Lowest power (for bit rates less than 32kbps). Low power (for bit rates between 32kbps and 64kbps). Normal operation (for bit rates greater than 64kbps). 24 CMX649 D/649/2 ...
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... VAD status changes. X Decoder is enabled and will generate periodic IRQs to indicate whether the PCM data is needed or available when transcoding. 1 Decoder is enabled and will generate periodic IRQs to indicate whether the ADM data is needed or available when transcoding. 25 CMX649 th the bit th the bit rate). D/649/2 ...
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... ADM estimator output summed with PCM interpolation filter output drives decoder output. The ADM and PCM signals can be input from any combination of RX DATA pin and C-BUS input registers Direct PCM test mode Interpolated PCM output. 26 Selected PCM Input Selected ADM Input CMX649 D/649/2 ...
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... Rate 6144/(3*Bit Rate) 27 Decay Time Constant (ms), Bit Rate in kbps 128/(Bit Rate) 256/(Bit Rate) 512/(Bit Rate) 1024/(Bit Rate) 2048/(Bit Rate) 4096/(Bit Rate) 8192/(Bit Rate) 16384/(Bit Rate) VAD Output CMX649 D/649/2 ...
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... Bluetooth compatible when running at 64kbps. Companding Rule Decay Time Constant (ms) 16/(3*Bit Rate) 24/(3*Bit Rate) 32/(3*Bit Rate) 48/(3*Bit Rate) 64/(3*Bit Rate) 96/(3*Bit Rate) Bluetooth compatible when running at 64kbps. 128/(3*Bit Rate 192/(3*Bit Rate) CMX649 D/649/2 ...
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... Time Constant (ms), Bit Rate in kbps 0 0 N/A (select for first order estimator (Signal Detection Register Value (DAC Full (Offset Register Value (DAC Full 29 1.5/Bit Rate 2.5/Bit Rate 4.5/Bit Rate 15 Threshold) 2 Scale Reference Voltage) 18 Voltage) 2 Scale Reference Voltage) CMX649 D/649/2 ...
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... ADM input comes from transcode feedback it will transcode from PCM to ADM. The PCM filter must be set to interpolate. In this mode the encode analog interface can be powered down since it is not used. (PCM to ADM transcoding input operation the bit rate). CMX649 th D/649/2 ...
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... Decay Time Constant)/32 Bit 1 VAD Output 0 Nominal VAD operation. 1 ADM bits are driven over VAD pin at the ADM bit rate (may be useful when transcoding or verifying proper application of the burst interface). 0 VAD output driven VAD output driven CMX649 D/649/2 ...
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... Bit 9 Bit Bluetooth compatible when running at 64kbps Bit Rate in kbps Minimum Step Bluetooth compatible when running at 64kbps. Companding Rule CMX649 D/649/2 ...
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... Time Constant)/ (Estimator Time Constant)/ (Estimator Time Constant)/8 Bit 2 Bit 1 Time Constant (ms), Bit Rate in kbps 0 0 N/A (select for first order estimator 1.5/Bit Rate 1 0 2.5/Bit Rate 1 1 4.5/Bit Rate 33 Bit Rate in kbps Loss Factor CMX649 D/649/2 ...
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... PCM. An interrupt can be enabled to inform a micro-controller when the register Input Test needs reloading. (Bits 7 – 0) 2003 CML Microsystems Plc (Signal Detection Register Value (DAC Full Scale (Offset Voltage) Register Value (DAC Full Scale 34 CMX649 15 Threshold) 2 Reference Voltage Reference Voltage) D/649/2 ...
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... The equation for the PCM register value is: 2003 CML Microsystems Plc -1 (Envelope Register Value (DAC Full Scale (Offset Register Value (DAC Full Scale (PCM Register Value (DAC Full Scale 35 15 voltage level) 2 Reference Voltage) 18 Voltage) 2 Reference Voltage) 15 voltage) 2 Reference Voltage) CMX649 D/649/2 ...
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... CML Microsystems Plc -1 (Envelope Register Value (DAC Full Scale (Offset Register Value (DAC Full Scale (PCM Register Value (DAC Full Scale 36 15 voltage level) 2 Reference Voltage) 18 Voltage) 2 Reference Voltage) 15 voltage) 2 Reference Voltage) CMX649 D/649/2 ...
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... The number of data bytes following an A/C byte is dependent on the value of the A/C byte. The most significant bit of the address or data is sent first. The C-BUS SERIAL_CLOCK input to the CMX649 originates from the host µC. CSN ...
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... Edge 1 rise 1 rise Rx_hold 75nS min Data Word Length Order and Byte Order msb first bits (m.s. byte first) msb first bits (m.s. byte first) Sync_hold 75nS min CMX649 70% 30 D/649/2 ...
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... Example CODEC Setups and Application Help Below are tabulated some applicable settings for the CLOCK DIVIDER CONTROL Register ($72) . Audio Switched Capacitor Filter Clock Settings (clock frequency in kHz) Crystal vs Audio Filter Divider Chart for CMX649 Yielding the Recommended ~256kHz SCF Clock Divider values Register bits ...
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... CML Microsystems Plc Bit Rate (kbps) Settings with Bit Rate Prescaler = 1 Crystal vs Divider chart for CMX649 1 2 2.25 2.625 001 010 011 31.250 27.778 23.810 31.500 28.000 24.000 32.000 28.444 24.381 62 ...
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... CML Microsystems Plc Crystal vs Divider chart for CMX649 1 2 2.25 2.625 001 010 011 20.833 18.519 15.873 21.000 18.667 16.000 21.333 18.963 16.254 29.400 26.133 22.400 31.250 27.778 23 ...
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... PCM out ($D0 $86 $B8) (reset default has $D7 $00 $00) // turn Scrambler and Descrambler off ($71 $00 $00 Make PLL run with input from data pad // internal RX and TX clocks // RX data input acting as analog input i.e. data filter and data slicer running // ($73 $00 $D2) 2003 CML Microsystems Plc 42 CMX649 D/649/2 ...
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... PCM buffered (3=uLaw 4=Alaw) //$70 $02 // decoder flow for input PCM plus transcode to ADM with offset null and output via VAD output. //$D0 $57 $02 //$D3 $00 $04 2003 CML Microsystems Plc 43 CMX649 D/649/2 ...
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... Operating Temperature Xtal Frequency 2003 CML Microsystems Plc pins SS Notes 44 Min. Max. Units -0.3 7 -30 +30 mA -20 +20 mA Min. Max. Units – 300 mW – 5.0 mW/°C – 800 mW – 13 mW/°C -55 +125 °C -40 +85 °C Min. Max. 2.7 5.5 -40 +85 4.0 16.0 CMX649 Units V °C MHz D/649/2 ...
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... CMX649 = -40 to Units µA µ µ kHz kHz dBmOp dBmOp st D/649/2 ...
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... ADM Codec MIC Amplifier Open Loop Gain Unity Gain Bandwidth Input Impedance Output Impedance (open loop) Distortion 2003 CML Microsystems Plc - 6 CMX649 - dB - MHz - D/649/2 ...
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... ADM Codec 7.1.3 (continued) C-BUS Timing Diagram 2003 CML Microsystems Plc Figure 14 C-BUS Timing Diagram 47 CMX649 D/649/2 ...
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... SERIAL_CLOCK pulses starting and ending at either polarity. 5. Maximum 30pF load on IRQN pin and each C-BUS interface line. These timings are for the CMX649, and allow faster transfers than the original C-BUS specification. For codec data interface timing specifications and diagrams please refer to section 6.2. ...
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... ADM Codec 7.2 Packaging Figure 15 20-Lead TSSOP Mechanical Outline: Order as part no. CMX649E3 Figure 16 20-Lead SOIC Mechanical Outline: Order as part no. CMX649D3 2003 CML Microsystems Plc 49 CMX649 D/649/2 ...
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... Industrial Building, Singapore 349307 Tel: +65 6745 0426 800 638 5577 Fax: +65 6745 2917 Sales: sg.sales@cmlmicro.com Technical Support: sg.techsupport@cmlmicro.com CMX649 No. 218, Tian Mu Road West, Tower 1, Unit 1008, Shanghai Kerry Everbright City, Zhabei, Shanghai 200070, China. Tel: +86 21 6317 4107 +86 21 6317 8916 ...