CMX649 CML Microcircuits, CMX649 Datasheet - Page 38

• Manufacturer Part Number: CMX649
• Description: ADM Codec
• Manufacturer: CML Microcircuits

ADM Codec
6.2
Clock generation (internal clock - Master mode) non burst mode
Synchronous operation (external clock – Slave mode)
Max Frame length : limited by burst clock to bit rate ratio only
Burst_CLK frequency : 5MHz max
Data word length : 8 or 16 bits
SYNC Delay : 0 Burst CLKs
SYNC Length : 1 – (data word length – 1 ) Burst CLKs
Words (slots) per frame : 1
Slot start references (from SYNC)
Tx and Rx clocks are tied together for burst mode. There is only one sync input.
Notes for Figure 13:
BURST CLOCK
RX_DATA
TX_DATA
2003 CML Microsystems Plc
In this example Bit 7 is the most significant bit.
Once started Rx and Tx data bits are continuously streaming so long as the SYNC pulse continues at
the PCM sample rate.
Configuration options support some variations of this timing diagram, e.g. data word length, without
affecting the timing shown.
The TX_DATA output may be high impedance between burst frames depending on bit 9 of CLK
SOURCE CONTROL Register ($73).
Line
RX DATA
TX DATA
SYNC
CODEC Data Interface
Configure to tri-state or
drive between frames.
Figure 13 Burst Interface Timing Diagram for Concatenated Byte Transfers
Sync_setup
75nS min
Directio
Output
Input
n
50nS max
Tx_delay,
Start at
Clk
Rx_setup
75nS min
1
1
7
7
Data Transition
6
6
Edge
rise
rise
5
5
Rx_hold
75nS min
38
4
4
Transmission
3
3
msb first
msb first
Order
2
2
1
1
8 or 16 bits (m.s. byte first)
8 or 16 bits (m.s. byte first)
Data Word Length
0
0
and Byte Order
Sync_hold
75nS min
7
7
6
6
CMX649
D/649/2
70%
30%