CMX649 CML Microcircuits, CMX649 Datasheet - Page 48

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CMX649

Manufacturer Part Number
CMX649
Description
ADM Codec
Manufacturer
CML Microcircuits
Datasheet
ADM Codec
t
t
t
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Notes:
These timings are for the CMX649, and allow faster transfers than the original C-BUS specification.
For codec data interface timing specifications and diagrams please refer to section 6.2.
C-BUS Timing (see Figure 14)
CSE
CSH
LOZ
HIZ
CSOFF
NXT
CK
CH
CL
CDS
CDH
RDS
RDH
2003 CML Microsystems Plc
1. Depending on the command, 1 or 2 bytes of COMMAND DATA are transmitted to the
2. Data is clocked into the peripheral on the rising SERIAL_CLOCK edge.
3. Commands are acted upon at the end of each command (rising edge of CSN).
4. To allow for differing µC serial interface formats C-BUS compatible ICs are able to work
5. Maximum 30pF load on IRQN pin and each C-BUS interface line.
CSN Enable to SClk high time
Last SClk high to CSN high time
SClk low to ReplyData Output Enable
Time
CSN high to ReplyData high impedance
CSN high time between transactions
Inter-byte time
SClk cycle time
SClk high time
SClk low time
Command Data setup time
Command Data hold time
Reply Data setup time
Reply Data hold time
peripheral MSB (Bit 7) first, LSB (Bit 0) last. REPLY DATA is read from the peripheral
MSB (Bit 7) first, LSB (Bit 0) last.
with SERIAL_CLOCK pulses starting and ending at either polarity.
48
Notes
Min.
100
100
200
200
100
100
0.0
1.0
75
25
50
0
Typ.
Max.
1.0
Unit
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
CMX649
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