FR65E Fujitsu Microelectronics, Inc., FR65E Datasheet - Page 20

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FR65E

Manufacturer Part Number
FR65E
Description
32-bit Microcontroller
Manufacturer
Fujitsu Microelectronics, Inc.
Datasheet
20
MB91307B
2. Internal Architecture
The FR series CPU uses a Harvard architecture with independent instruction bus and data bus. The instruction
bus (I-BUS) is connected to an on-chip instruction cache. a 32-bit
bus (F-BUS) to provide an interface between the CPU and peripheral resources. The Harvard
bus converter is connected to the both the I-BUS and D-BUS as an interface between the CPU and bus controller.
Instruction
cache
RAM
I address
I data
F address
F data
D bus
Peripherals resource
R-bus
Internal Architecture
Bus converter
FRex CPU
32 bit
16 bit
D address
D data
16
I bus
16-bit bus converter is connected to the
32
32
32
32
32
32
X-bus
Bus controller
Princeton
converter
Harvard
bus
Princeton

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