ACS8944 Semtech Corporation, ACS8944 Datasheet - Page 14

• Manufacturer Part Number: ACS8944
• Description: Jitter Attenuating, Multiplying Phase Locked Loop for Oc-12/stm-4
• Manufacturer: Semtech Corporation

Input and Output Interface Terminations
Interfacing to either the same type or electrically different
interface types is illustrated by the following circuit
diagrams, covering translation from LVDS to LVPECL.
The example of Figure 12 shows LVPECL to LVPECL
terminations with D.C. coupling, so that the ACS8944
sees an equivalent load of around 50 Ω from the R3, R4,
R5, R6 resistor arrangement at the receiver end.
Figure 12 LVPECL Output - DC Coupled to LVPECL or LVDS
Receiver
Input/Output Timing
Figure 14 Timing Diagrams
Revision 3/November 2006 © Semtech Corp.
ADVANCED COMMUNICATIONS
1) Input to Output
2)
Delay
Power-up Sequence
VDD -1.0 V
VDD -1.4 V
VDD -1.8 V
ASC8944 or similar
LVPECL Output
OUTP
OUTN
(90% VDD)
VDD
OUTP
Transmission Line
RESETB
Input frequency must be within 400 ppm of nominal
before releasing reset
OUTY
CLKX
CLKX
VDD
Time
130R
82R
t
PDIO
t
VDD
RPW
VSS
130R
82R
These resistors may
be integrated on-chip
ACS8944 or similar
LVPECL/LVDS receiver
F8944D_015LVPECL2LVPECL_03
t
FT
Start of Frequency
Tuning Algorithm
FINAL
Page 14
The preferred termination circuitry for the LVDS signals
between the ACS8525/26/27 and the ACS8944 LVPECL
is shown in Figure 13. The bias for the LVPECL input is set
for A.C. inputs at a mid point of approximately 2 V (with a
3.3 V VDD), as opposed to a normal D.C. coupled bias of
VDD - 2 V. This is due to the push-pull nature of an A.C.
coupled signal.
Figure 13 Generic LVDS - AC Coupled to LVPECL Receiver
LVDS
Output
Device
F8944D_017LVDS2LVPECL_02
OUTN
OUTP
Transmission
Line Impedance
50 Ohms
R1
100
ACS8944 JAM PLL
C1
220nF
C2
220nF
R5
2K7
F8944D 021IP OPTi i g 01
R3
4K3
VDD
R2
2K7
LVPECL
INPUT
R4
4K3
DATASHEET
www.semtech.com
GND
CLKN
CLKP
JAM PLL