ACS8944 Semtech Corporation, ACS8944 Datasheet - Page 5

• Manufacturer Part Number: ACS8944
• Description: Jitter Attenuating, Multiplying Phase Locked Loop for Oc-12/stm-4
• Manufacturer: Semtech Corporation

Table 3 Functional Pins (cont...)
Note...I = Input, O = Output, P = Power, LVTTL/LVCMOS
with pull-down resistor
The ACS8944 is a low jitter integrated PLL for clock
dejittering and clock rate translation, meeting the jitter
requirements for SONET up to and including OC-12
(622.08 MHz systems). It is compliant to the relevant ITU,
Telcordia/Bellcore and ETSI standards for at least OC-3
(155.52 MHz) and OC-12 (622.08 MHz) - equivalent to
the corresponding STM-1 and STM-4 rates.
It can be configured for a range of applications using a
minimal number of external components and is available
in a small form factor QFN48 package at 7 mm x 7 mm x
0.9 mm outer dimensions.
Input
The ACS8944 has a single, LVPECL, differential input
(CLKN/P, pins 27 and 28). It is designed to operate with
any of 19.44 MHz, 38.88 MHz, 77.76 MHz or
155.52 MHz input references, and can pull in an input
which is within ±400 ppm of these spot frequencies.
Input Configuration
The input must be configured for the expected input
frequency. This is achieved by connecting the EXT[3:1]
pins, to the configuration pins or to power (VDD) or ground
Revision 3/November 2006 © Semtech Corp.
Description
ADVANCED COMMUNICATIONS
24
27
28
35
36
40
46
Pin No.
EXT3
CLKN
CLKP
VCP
VCN
RESETB
OP_FSEL
Symbol
I/O
I/O
I/O
I
I
I
I
I
LVTTL/LVCMOS
LVTTL/LVCMOS
Schmitt Trigger
LVCMOS
LVPECL
LVPECL
Analog
Analog
LVTTL/
Type
D
D
U
Input frequency configuration pin. See Table 4.
Input reference clock to which the PLL will phase and frequency lock (negative pin of
differential pair, partnered with pin 28). Can accept 19.44 MHz, 38.88 MHz, 77.76 MHz or
155.52 MHz to within ±400 ppm.
Input reference clock to which the PLL will phase and frequency lock (positive pin of
differential pair, partnered with pin 27). Can accept 19.44 MHz, 38.88 MHz, 77.76 MHz or
155.52 MHz to within ±400 ppm.
Connection for external loop filter components. This is the differential control voltage input
to the internal VCO and the internal differential charge pump output.
Connection for external loop filter components. This is the differential control voltage input
to the internal VCO and the internal differential charge pump output.
Active low reset signal with pull up and Schmitt type input. Used to apply a Power On Reset
(POR) signal during system initialization. Should be connected via a capacitor to ground.
Output Frequency Select Pin. Used with the Output Frequency Configuration pins (pins 13
to 16) to configure the output frequency (on power-up/reset) of the differential output
OUT(N/P). See Table 5.
U
= LVTTL/LVCMOS input with pull-up resistor, LVTTL/LVCMOS
FINAL
Page 5
(VSS), in accordance with the configuration scheme in
Table 4, e.g. for an expected input of 155.52 MHz,
connect EXT1 to VSS, EXT2 to CFG_OUT1 and EXT3 to
CFG_OUT3.
Table 4 Input Frequency Selection
Output
The ACS8944 has a single, LVPECL, differential output
(OUTN/P, pins 2 and 3).
The frequency of the output is determined by the wiring of
OP_FSEL to the appropriate CFG_OUT pin in accordance
with Table 5.
19.44 MHz
38.88 MHZ
77.76 MHz
155.52 MHz
For Expected
Frequency
Input
of
Description
CFG_OUT3
CFG_OUT0
EXT1
VDD
VSS
ACS8944 JAM PLL
CFG_OUT1
CFG_OUT1
Connect
EXT2
VDD
VDD
to
D
= LVTTL/LVCMOS input
DATASHEET
www.semtech.com
CFG_OUT3
CFG_OUT3
CFG_OUT3
CFG_OUT3
EXT3