ACS8944 Semtech Corporation, ACS8944 Datasheet - Page 4

• Manufacturer Part Number: ACS8944
• Description: Jitter Attenuating, Multiplying Phase Locked Loop for Oc-12/stm-4
• Manufacturer: Semtech Corporation

Table 2 Internally Connected (IC)/ Not Connected (NC) Pins
Table 3 Functional Pins
Revision 3/November 2006 © Semtech Corp.
ADVANCED COMMUNICATIONS
18,19,
37, 41
42
4, 5,
6, 7,
8, 9,
10, 11,
12, 20,
21, 30,
31, 32,
33, 44,
45, 47,
48
2
3
13
14
15
16
17
22
23
Pin No.
Pin No.
IC1, IC2,
IC3, IC4,
IC5
NC1, NC2,
NC3, NC4,
NC5, NC6,
NC7, NC8,
NC9, NC10,
NC11, NC12
NC13, NC14,
NC15, NC16,
NC17, NC18,
NC19
OUTN
OUTP
CFG_OUT0
CFG_OUT1
CFG_OUT2
CFG_OUT3
LOCKB
EXT1
EXT2
Symbol
Symbol
I/O
I/O
O
O
O
O
O
O
O
I
I
-
-
-
LVTTL/LVCMOS
LVTTL/LVCMOS
LVTTL/LVCMOS
LVTTL/LVCMOS
LVTTL/LVCMOS
LVTTL/LVCMOS
LVPECL
LVPECL
Analog
Type
Type
-
-
-
D
D
Internally connected. Connect to ground.
Internally connected. Connect to VDD.
Not connected. Leave to float.
LVPECL differential output at a rate from 19.44 MHz up to 155.52 MHz. Partnered with
pin 3. See pin 3 description for more detail.
LVPECL differential output at a rate from 19.44 MHz up to 155.52 MHz. Partnered with
pin 2. The output frequency selection is preset by externally connecting OP_FSEL pin (pin
46), to one from a set of four output frequency pins CFG_OUT[3:0] (Pins 16, 15, 14 and
13); which, on reset will give a corresponding generated output frequency of 19.44 MHz,
38.88 MHz, 77.76 MHz, or 155.52 MHz.
Configuration pin used to set input reference frequency for CLK (N and P) and output clock
frequency for OUT (N and P) used in conjunction with pins 14, 15, 16, and 46 as defined in
Tables 4 and 5.
Configuration pin used to set input reference frequency for CLK (N and P) and output clock
frequency for OUT (N and P) used in conjunction with pins 13, 15, 16 and 46 as defined in
Tables 4 and 5.
Configuration pin used to set input reference frequency for CLK (N and P) and output clock
frequency for OUT (N and P) used in conjunction with pins 13, 14, 16 and 46 as defined in
Tables 4 and 5.
Configuration pin used to set input reference frequency for CLK (N and P) and output clock
frequency for OUT (N and P) used in conjunction with pins 13, 14, 15 and 46 as defined in
Tables 4 and 5.
Lock detect output. This is a pulse width modulated output current, with each pulse
typically +10 µA. The output produces a pulse with a width in proportion to the phase error
seen at the internal phase detector. This pin should be connected via an external parallel
capacitor and resistor to ground. The pin voltage will then give an indication of phase lock:
When low, the device is phase locked; when high the device has frequent large phase
errors and so is not phase locked. The value of the RC components used determines the
time and level of consistency required for lock indication.
Input frequency configuration pin. See Table 4.
Input frequency configuration pin. See Table 4.
FINAL
Page 4
Description
Description
ACS8944 JAM PLL
DATASHEET
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