USB3250 Standard Microsystems Corporation, USB3250 Datasheet - Page 30

• Manufacturer Part Number: USB3250
• Description: Usb2.0 PHY IC
• Manufacturer: Standard Microsystems Corporation

Revision 1.5 (03-24-06)
RXDATA[7:0]
RXDATA[7:0]
RXACTIVE
RXERROR
RXACTIVE
RXERROR
RXVALID
RXVALID
DP/DM
DP/DM
CLK60
CLK60
Note 7.2
Note 7.3
Figure 7.10 Receive Timing for Data (with CRC-16 in 8-bit mode)
Figure
it is in HS mode. When a HS/FS Macrocell is in FS Mode (8-bit mode) there are
approximately 40 CLK60 cycles every byte time. The Receive State Machine assumes that
the SIE captures the data on the RXDATA bus if RXACTIVE and RXVALID are asserted.
In FS mode, RXVALID will only be asserted for one CLK60 per byte time.
Figure
byte long. The SYNC pattern received by a device can vary in length. These figures
assume that all but the last 12 bits have been consumed by the hubs between the device
and the host controller.
Figure 7.11 Receive Timing for Setup Packet (8-bit mode)
SYNC
7.10,
7.10,
Figure 7.11
Figure 7.11
PID
DATA
SYNC
DATASHEET
PID
and
and
Figure 7.12
DATA
Figure 7.12
30
DATA
PID
CRC-5 Computation
EOP
EOP
DATA
are timing examples of a HS/FS Macrocell when
PID
the SYNC pattern on DP/DM is shown as one
SMSC GT3200, SMSC USB3250
USB2.0 PHY IC
Datasheet