USB3250 Standard Microsystems Corporation, USB3250 Datasheet - Page 40

• Manufacturer Part Number: USB3250
• Description: Usb2.0 PHY IC
• Manufacturer: Standard Microsystems Corporation

Revision 1.5 (03-24-06)
8.10
PARAMETER
TIMING
T9
Note 8.3
Note 8.4
Note 8.5
If reset is entered from a suspended state, the internal oscillator and clocks of the transceiver are
assumed to be powered down.
chirp generated by the device.
When reset is entered from a suspended state (J to SE0 transition reported by LINESTATE),
SUSPENDN is combinatorially negated at time T0 by the SIE. It takes approximately 5 milliseconds
for the transceiver's oscillator to stabilize. The device does not generate any transitions of the CLK60
signal until it is "usable" (where "usable" is defined as stable to within ±10% of the nominal frequency
and the duty cycle accuracy 50±5%).
The first transition of CLK60 occurs at T1. The SIE then sets OPMODE to Disable Bit Stuffing and
NRZI encoding, XCVRSELECT to HS mode, and must assert a Chirp K for 66000 CLK60 cycles to
ensure a 1ms minimum duration. If CLK60 is 10% fast (66MHz) then Chirp K will be 1.0ms. If CLK60
is 10% slow (54 MHz) then Chirp K will be 1.2ms. The 5.6ms requirement for the first CLK60 transition
after SUSPENDN, ensures enough time to assert a 1ms Chirp K and still complete before T3. Once
the Chirp K is completed (T3) the SIE can begin looking for host chirps and use CLK60 to time the
process. At this time, the device follows the same protocol as in section 8.9 for completion of the High
Speed Handshake.
HS Detection Handshake - Suspend Timing
The earliest time at which host port may end reset.
The latest time, at which the device may remove the
DP pull-up and assert the HS terminations, reverts to
HS default state.
T0 may be up to 4ms after HS Reset T0.
The SIE must use LINESTATE to detect the downstream port chirp sequence.
Due to the assertion of the HS termination on the host port and FS termination on the
device port, between T1 and T7 the signaling levels on the bus are higher than HS
signaling levels and are less than FS signaling levels.
Table 8.7 Reset Timing Values (continued)
DESCRIPTION
Figure 8.6
DATASHEET
40
shows how CLK60 is used to control the duration of the
HS Reset T0 + 10ms
SMSC GT3200, SMSC USB3250
VALUE
USB2.0 PHY IC
Datasheet