LM27262 National Semiconductor Corporation, LM27262 Datasheet - Page 9

• Manufacturer Part Number: LM27262
• Description: Intel Cpu Core Voltage Regulator Controller For VRD10 Compatible PCS
• Manufacturer: National Semiconductor Corporation

REFINT
PHASES
LOGIC OUTPUTS: DRIVEx
VIDPGD
Symbol
Electrical Characteristics
Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the
device is guaranteed. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics table.
Note 2: The maximum allowable power dissipation is calculated by using P
ambient temperature, and θ
for T
dissipation of more power. The Absolute Maximum power dissipation should be de-rated by 12.5mW per ˚C above 25˚C ambient. The LM27262 actively limits its
junction temperature to about 165˚C.
Note 3: For detailed information on soldering plastic small-outline packages, refer to the Packaging Databook available from National Semiconductor Corporation.
Note 4: For testing purposes, ESD was applied using the human-body model, a 100pF capacitor discharged through a 1.5kΩ resistor.
Note 5: All limits are guaranteed at room temperature (standard face type) and at temperature extremes (bold face type). All room temperature limits are 100%
production tested. All limits at temperature extremes are guaranteed via correlation using Statistical Quality Control (SQC) methods. All limits are used to calculate
Average Outgoing Quality Level (AOQL).
Note 6: A “typical” specification is the center of characterization data distribution taken with T
JMAX
, T
A
VRON De-assertion
Delay
REFINT Leakage
Current
Logic Low Input
Voltage
Logic High Input
Voltage
PHASES Leakage
Current
PHASES Open Circuit
Voltage
Logic Low Max Input
Voltage
Logic High Min Input
Voltage
Output High Voltage
Output Low Voltage
Low-to-High Transition
Time
High-to-Low Transition
Time
VIDPGD Output Max
Low Voltage
VIDPGD Leakage
Current
VIDPGD Assertion
Delay
VIDPGD De-assertion
Delay
, and θ
JA
Parameter
respectively. The θ
JA
is the junction-to-ambient thermal resistance of the specified package. The 1.56W rating results from using 150˚C, 25˚C, and 80˚C/W
JA
Delay of VRON falling edge by the internal logic
REFINT = 3.3V or GND
V
V
10MΩ to Ground
Relative to Vcc (5V nominal)
Output Source Current is 10 mA
Output Source Current is 0 mA (no load)
Output Sink Current is 10 mA
10% to 90% of V
C
90% to 10% of V
C
VIDPGD sinking 4mA (open drain)
VIDPGD = 5.5V
VRON assertion to VIDPGD assertion
(SOFTCAP = 0.01µF)
VRON de-assertion to VIDPGD de-assertion
of 90˚C/W represents the worst-case condition with no heat sinking of the 48-Pin TSSOP. Heat sinking allows the safe
PHASES
PHASES
LOAD
LOAD
= 50pF
= 50pF
(Note 5)
=0V
= 3.3V
,
(Note 6) V
CC
CC
Conditions
5V,
5V,
Dmax
CC
= (T
9
5V = 5V unless otherwise specified. (Continued)
JMAX
- T
A
) /θ
A
= T
JA
J
, where T
= 25˚C. Typical data are not guaranteed.
JMAX
Min
is the maximum junction temperature, T
0.17
Typ
- 25
-0.2
0.5
3.0
2.8
0.2
3.5
4.5
0.3
±
50
20
20
50
4
1
2
2
Max
0.25
10
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nsec
Unit
A
ms
µA
µA
µA
µA
ns
ns
ns
V
V
V
V
V
V
V
V
is the