ATA5423 ATMEL Corporation, ATA5423 Datasheet - Page 29

• Manufacturer Part Number: ATA5423
• Manufacturer: ATMEL Corporation

Figure 4-3.
4.2
4841A–RKE–02/05
Basic Clock Cycle of the Digital Circuitry
(Control Register 3)
N_RESET
Clock Timing
CLK_ON
VSOUT
CLK
V
The complete timing of the digital circuitry is derived from one clock. As shown in
on page
a divider.
T
The clock cycle of the bit check and the TX baud rate depends on the selected baud–rate range
(BR_Range) which is defined in control register 6 (see
is defined in control register 4 (see
the following formulas for further reference:
BR_Range
f
DCLK
Thres_2
DCLK
• Timing of the polling circuit including bit check
• TX baud rate
= 2.38 V (typ)
=
controls the following application relevant parameters:
f
---------- -
27, this clock cycle T
XTO
16
V
Thres_1
= 2.3 V (typ)
DCLK
is derived from the crystal oscillator (XTO) in combination with
Table 7-13 on page
ATA5423/25/28/29 [Preliminary]
BR_Range 0: T
BR_Range 1: T
BR_Range 2: T
BR_Range 3: T
XDCLK
XDCLK
XDCLK
XDCLK
40). This clock cycle T
Table 7-20 on page
= 8
= 4
= 2
= 1
T
T
T
T
DCLK
DCLK
DCLK
DCLK
X
X
X
X
42) and XLim which
Lim
Lim
Lim
Lim
XDCLK
is defined by
Figure 4-2
29