ATA5423 ATMEL Corporation, ATA5423 Datasheet - Page 58

• Manufacturer Part Number: ATA5423
• Manufacturer: ATMEL Corporation

Figure 9-6.
Figure 9-7.
9.1.6
58
Bit-check counter
Bit-check counter
ATA5423/25/28/29 [Preliminary]
Duration of the Bit Check
RX_ACTIVE
RX_ACTIVE
Demod_Out
Demod_Out
(Lim_min = 14, Lim_max = 24)
(Lim_min = 14, Lim_max = 24)
Timing Diagram for Failed Bit Check (Condition CV_Lim < Lim_min)
Timing Diagram for Failed Bit Check (Condition: CV_Lim
Bit check
Bit check
Start-up mode
Start-up mode
T
T
Startup_Sig_Proc
Startup_Sig_Proc
If no transmitter is present during the bit check, the output of the ASK/FSK demodulator delivers
random signals. The bit check is a statistical process and T
fore, an average value for T
the selected baud rate range and on T
T
Bit–check
0
0
, resulting in a lower current consumption in RX polling mode.
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 101112
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 101112
Bit check failed (CV_Lim < Lim_min)
Bit-check mode
T
Bit-check
Bit–check
1/2 Bit
Bit-check mode
Bit check failed (CV_Lim
T
Bit-check
is given in the electrical characteristics. T
1/2 Bit
XDCLK
131415161718192021222324
. A higher baud–rate range causes a lower value for
Lim_max)
Lim_min)
Sleep mode
Bit–check
T
Sleep
0
varies for each check. There-
Sleep mode
T
Sleep
0
Bit–check
4841A–RKE–02/05
depends on