ATA5423 ATMEL Corporation, ATA5423 Datasheet - Page 37
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ATA5423
Manufacturer Part Number
ATA5423
Description
Manufacturer
ATMEL Corporation
Datasheet
1.ATA5423.pdf
(97 pages)
- Current page: 37 of 97
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4841A–RKE–02/05
After the transceiver is turned on via pin PWR_ON = High, T1 = Low, T2 = Low, T3 = Low,
T4 = Low or T5 = Low or the voltage at pin VAUX V
are in the default state.
Figure 7-1.
Baud 1 Baud 0
BitChk
MSB
NFSK
FR12
ASK/
FR6
ST5
IR1
1
-
BitChk
FR11
Register Structure
Sleep
FR5
ST4
IR0
0
-
4
AVCC
FR10
max5
Sleep
Lim_
min5
Lim_
FR4
ST3
_EN
-
3
max4
Sleep
Lim_
min4
Lim_
FR3
FR9
ST2
FS
-
2
max3
Sleep
Lim_
min3
Lim_
FR2
FR8
ST1
ATA5423/25/28/29 [Preliminary]
-
1
Power
OPM1
max2
Sleep
Lim_
min2
Lim_
FR1
FR7
_On
0
XSleep
OPM0
max1
Low_
VSO
Lim_
min1
Lim_
FR0
UT_
Batt
EN
VAUX
MODE
MODE
P_On
CLK_
max0
LSB
XLim
_Aux
Lim_
min0
Lim_
ON
T_
P_
> 3.5 V (typically), the control registers
Status Register (ADR 8)
TX/RX Data Buffer:
Control Register 1 (ADR 0)
Control Register 2 (ADR 1)
Control Register 3 (ADR 2)
Control Register 4 (ADR 3)
Control Register 5 (ADR 4)
Control Register 6 (ADR 5)
16
8 Bit
37
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