ATA8742 ATMEL Corporation, ATA8742 Datasheet - Page 140

• Manufacturer Part Number: ATA8742
• Manufacturer: ATMEL Corporation

140
ATA8742
Figure 23-3. Three-wire Mode, Timing Diagram
The Three-wire mode timing is shown in
USCK cycle reference. One bit is shifted into the USI Shift Register (USIDR) for each of these
cycles. The USCK timing is shown for both external clock modes. In External Clock mode 0
(USICS0 = 0), DI is sampled at positive edges, and DO is changed (Data Register is shifted by
one) at negative edges. External Clock mode 1 (USICS0 = 1) uses the opposite edges versus
mode 0, i.e., samples data at negative and changes the output at positive edges. The USI clock
modes corresponds to the SPI data mode 0 and 1.
Referring to the timing diagram
steps:
1. The Slave device and Master device sets up its data output and, depending on the proto-
2. The Master generates a clock pulse by software toggling the USCK line twice (C and D).
3. Step 2 is repeated eight times for a complete register (byte) transfer.
4. After eight clock pulses (i.e., 16 clock edges) the counter will overflow and indicate that
col used, enables its output driver (mark A and B). The output is set up by writing the
data to be transmitted to the Serial Data Register. Enabling of the output is done by set-
ting the corresponding bit in the port Data Direction Register. Note that point A and B
does not have any specific order, but both must be at least one half USCK cycle before
point C where the data is sampled. This must be done to ensure that the data setup
requirement is satisfied. The 4-bit counter is reset to zero.
The bit value on the slave and master’s data input (DI) pin is sampled by the USI on the
first edge (C), and the data output is changed on the opposite edge (D). The 4-bit counter
will count both edges.
the transfer is completed. The data bytes transferred must now be processed before a
new transfer can be initiated. The overflow interrupt will wake up the processor if it is set
to Idle mode. Depending of the protocol used the slave device can now set its output to
high impedance.
CYCLE
USCK
USCK
DO
DI
( Reference )
A
B
MSB
MSB
C
1
D
(Figure 23-3 on page
2
6
6
3
5
5
Figure 23-3 on page
4
4
4
140), a bus transfer involves the following
5
3
3
6
140. At the top of the figure is a
2
2
7
1
1
LSB
LSB
8
9151A–INDCO–07/09
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