ATA8742 ATMEL Corporation, ATA8742 Datasheet - Page 32

• Manufacturer Part Number: ATA8742
• Manufacturer: ATMEL Corporation

13.2.1
32
ATA8742
Data Memory Access Times
When using register indirect addressing modes with automatic pre-decrement and post-incre-
ment, the address registers X, Y, and Z are decremented or incremented.
The 32 general purpose working registers, 64 I/O Registers, and the 128/256/512 bytes of inter-
nal data SRAM in the ATtiny24/44/84 are all accessible through all these addressing modes.
The Register File is described in
Figure 13-2. Data Memory Map
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clk
page
Figure 13-3. On-chip Data SRAM Access Cycles
32.
Address
clk
Data
Data
WR
CPU
RD
(128/256/512 x 8)
64 I/O Registers
Data Memory
Internal SRAM
Compute Address
32 Registers
“General Purpose Register File” on page
T1
Memory Access Instruction
0x0DF/0x015F/0x025F
0x0000 - 0x001F
0x0020 - 0x005F
0x0060
Address valid
T2
CPU
cycles as described in
Next Instruction
T3
26.
9151A–INDCO–07/09
Figure 13-3 on