TMC2072 Fairchild Semiconductor, TMC2072 Datasheet - Page 6

• Manufacturer Part Number: TMC2072
• Description: Genlocking Video Digitizer
• Manufacturer: Fairchild Semiconductor

TMC2072
Pin Definitions
6
Pin Name
LDV
EXT PXCK
PXCK SEL
Digital Video
GHSYNC
GVSYNC
CVBS
FID[0]
FID[1]
SA[2:0]
SDA
SCL
P l/O
7-0
Pin Number
30-28, 25-21
3-1
40
94
86
32
33
35
36
(continued)
4
5
Pin Type
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
R-bus
R-bus
Pixel clock output. Delayed pixel clock output. LDV runs at 1/2 the
rate of PXCK and its rising edge is useful for transferring CVBS
digital video from the TMC2072 to the TMC22x9x Digital Video
Encoders.
External PXCK input. Input for external PXCK clock source.
PXCK source select. Select input for internal or external PXCK.
When HIGH, the internally generated line-locked PXCK is selected.
When LOW, the external PXCK source is enabled.
Horizontal sync output. When the TMC2072 is locked to incoming
video, the GHSYNC pin provides a negative-going pulse after the
falling edge of each horizontal sync pulse. When the device is
locked to a stable video signal, there is a fixed number of PXCK
clock cycles between adjacent falling edges of GHSYNC. If no video
signal is present and LEADLAG is less than 4A(hex), the TMC2072
will output normal, evenly-spaced horizontal pulses. If no video
signal is present and LEADLAG exceeds 88(hex), the TMC2072 will
omit every eighth Hsync pulse. As LEADLAG is increased from 49h
to 89h, seven out of every eight Hsyncs will be unaffected, but the
eighth will shrink by one clock cycle per LSB step, until it disappears
entirely at 89h.
Vertical sync output. When the TMC2072 is locked to incoming
video, the GVSYNC pin provides a negative-going edge after the
start of the first vertical sync pulse of a vertical blanking interval. If
no video signal is present on the selected input pin, GVSYNC will
remain continuously at logic high, until a signal is selected and lock
is reestablished. A system designer requiring a free-running vertical
sync may wish to provide this with an external pixel counter.
Composite output bus. 8-bit composite video data are output on
this bus at 1/2 the PXCK rate. During horizontal sync, field ID,
subcarrier frequency, and subcarrier phase are available on this
bus.
Odd/even (“top/bottom”) field flag. LOW denotes the first field of a
video frame; HIGH, the second.
Bruch blanking flag. In PAL, LOW denotes a frame with burst
blanked on line 310, whereas HIGH denotes burst detected on line
310. FID[1] is valid only in PAL and only when FID[0] is high and
should be interpreted as follows:
R-bus chip address, 3 LSBs. Full 7-bit address = {1, 0, 0, 0, SA[2],
SA[1], SA[0]}
R-bus bidirectional data line.
R-bus clock line (input/slave only)
FID[1:0]
01
11
PAL Field Number
II or VI
IV or VIII
Function
PRODUCT SPECIFICATION
REV. 1.0.4 6/19/01