TMC2072 Fairchild Semiconductor, TMC2072 Datasheet - Page 7

• Manufacturer Part Number: TMC2072
• Description: Genlocking Video Digitizer
• Manufacturer: Fairchild Semiconductor

PRODUCT SPECIFICATION
Pin Definitions
REV. 1.0.4 6/19/01
Pin Name
RESET
INT
VALID
BURL
Analog Interface
V
COMP
R
PLL Filter
DDS OUT
PFD IN
C
Power Supply
V
V
Ground
A
D
REF
DDA
DD
GND
B
BYP
GND
, R
T
69, 72, 74, 81, 89
6, 18, 26, 42, 44,
8, 16, 27, 38, 39,
48, 92, 98, 100
49, 51, 52, 60,
50, 55, 63, 67,
41, 46, 47, 90,
Pin Number
64, 73, 87
57, 68
95-97
17
34
31
70
88
82
77
75
(continued)
7
Pin Type
+1.23 V
CMOS
0.1 F
0.1 F
0.0 V
0.0 V
TTL/
1 F
+5 V
+5 V
TTL
TTL
TTL
Master reset input. Bringing RESET LOW forces the internal state
machines to their starting states, loads the Control Register with
default values, and disables outputs. Bringing RESET HIGH restarts
the TMC2072 in its default mode.
Interrupt output. This output is LOW if the internal horizontal phase
lock loop is unlocked with respect to incoming video for 128 or more
lines per field. After lock is established, INT goes HIGH.
HSYNC locked flag. Hsync locked flag. When high, this output
indicates that the most recent incoming horizontal sync has been
detected within ±16 pixels of its expected position. It goes low if no
sync is encountered during this ±16-pixel window, as during a
typical VCR headswitch line. Once the chip has locked to a clean
video source, this flag should remain high continuously. If the chip
has locked to a VCR, this flag will typically go low for one (or
sometimes two) lines at the bottom of each field.
Burst lock flag. When high, this output indicates that the chip’s
internal subcarrier synthesizer is phase-aligned with the current
line’s incoming chroma burst. The flag goes low when the internal
and external phases diverge.
V
reference is used, this pin should be decoupled to A
here, overriding the internal reference source.
Compensation capacitor. Compensation for DDS D/A converter
circuitry. This pin should be decoupled to V
capacitor.
A/D V
references. These pins should be decoupled to A
capacitor.
Internal DDS output. Analog output from the internal Direct Digital
Synthesizer D/A converter, at 1/9 the PXCK frequency.
Horizontal PLL input. Analog input to the Phase/Frequency
Detector of the horizontal phase-locked loop.
Comparator bypass. Decoupling point for the internal comparator
reference of the Phase/Frequency Detector. This pin should be
decoupled to A
Analog power supply. Positive power supply to analog section.
All pins must be connected.
Digital power supply. Positive power supply to digital section.
All pins must be connected.
Analog ground. Ground for analog section. All pins must be
connected.
Digital ground. Ground for digital section. All pins must be
connected.
F capacitor. An external +1.2 Volt reference may be connected
REF
REF
input/output. +1.23 Volt reference. When the internal voltage
decoupling. Decoupling points for A/D converter voltage
GND
with a 0.1 F capacitor.
Function
DDA
with a 0.1 F
GND
GND
with a 0.1 F
with a 0.1
TMC2072
7