MAX5876 Maxim Integrated Products, MAX5876 Datasheet - Page 14

• Manufacturer Part Number: MAX5876
• Description: Dual DAC with LVDS Inputs
• Manufacturer: Maxim Integrated Products

12-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
Table 2. DAC Output Code Table
The TORB input selects between two’s-complement or
offset binary digital input data. Set TORB to a CMOS-
logic-high level to indicate a two’s-complement input for-
mat. Set TORB to a CMOS-logic-low level to indicate an
offset binary input format.
The MAX5876 also features an active-high power-down
mode that reduces the DAC’s digital current consump-
tion from 33mA to less than 5µA and the analog current
consumption from 83mA to less than 2µA. Set PD high
to power down the MAX5876. Set PD low for normal
operation.
When powered down, the MAX5876 reduces the overall
power consumption to less than 16µW. The MAX5876
requires 10ms to wake up from power-down and enter
a fully operational state. The PD integrated pulldown
resistor activates the MAX5876 if PD is left floating.
Figure 5. Simplified LVDS-Compatible Digital Input Structure
14
B11N–B0N,
B11P–B0P,
SELIQP
SELIQN
______________________________________________________________________________________
OFFSET BINARY
0000 0000 0000
0111 1111 1111
1111 1111 1111
CMOS-Compatible Digital Inputs
110Ω
Input Data Format Select (TORB)
MAX5876
DIGITAL INPUT CODE
Power-Down Operation (PD)
CLOCK
D
D
Q
Q
TWO’S COMPLEMENT
1000 0000 0000
0000 0000 0000
0111 1111 1111
TO
DECODE
LOGIC
The MAX5876 features a flexible differential clock input
(CLKP, CLKN) with a separate supply (AV
achieve optimum jitter performance. Use an ultra-low
jitter clock to achieve the required noise density. Clock
jitter must be less than 0.5ps
fied noise density. For that reason, the CLKP/CLKN
input source must be designed carefully. The differen-
tial clock (CLKN and CLKP) input can be driven from a
single-ended or a differential clock source. Differential
clock drive is required to achieve the best dynamic
performance from the DAC. For single-ended opera-
tion, drive CLKP with a low noise source and bypass
CLKN to GND with a 0.1µF capacitor.
Figure 6 shows a convenient and quick way to apply a
differential signal created from a single-ended source
(e.g., HP 8662A signal generator) and a wideband trans-
former. Alternatively, these inputs can be driven from a
CMOS-compatible clock source; however, it is recom-
mended to use sinewave or AC-coupled differential
ECL/PECL or LVDS drive for best dynamic performance.
Figure 6. Differential Clock-Signal Generation
CLOCK SOURCE
(e.g., HP 8662A)
SINGLE-ENDED
PERFORMS SINGLE-ENDED-TO-
WIDEBAND RF TRANSFORMER
DIFFERENTIAL CONVERSION
1:1
Applications Information
I
OUTFS
OUT_P
I
OUTFS
0
GND
/ 2
RMS
25Ω
25Ω
for meeting the speci-
0.1µF
0.1µF
CLK Interface
I
OUTFS
www.DataSheet4U.com
OUT_N
I
OUTFS
TO DAC
0
/ 2
CLK
CLKP
CLKN
) to