MCIMX35 Motorola Semiconductor Products, MCIMX35 Datasheet - Page 30

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MCIMX35

Manufacturer Part Number
MCIMX35
Description
Manufacturer
Motorola Semiconductor Products
Datasheet

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4.7.3
There are three PLLs inside the MCIMX35, all based on the same PLL design. The reference clock for
these PLLs is normally generated from an external 24-MHz crystal connected to an internal oscillator via
EXTAL24M and XTAL24 pads. It is also possible to connect an external 24-MHz clock directly to
EXTAL24M, bypassing the internal oscillator.
DPLL specifications are listed in
4.7.4
ETM is an ARM protocol. The timing specifications in this section are given as a guide for a test point
access (TPA) that supports TRACECLK frequencies up to 133 MHz.
Figure 6
30
1
Reference Clock frequency
Max. allowed reference clock phase
noise
Frequency lock time (FOL mode or
non-integer MF)
Phase lock time
Max. allowed PL voltage ripple
There are two PLL are used in the MCIMX35, MPLL and PPLL. Both are based on same DPLL design.
MCIMX35 (i.MX35) Multimedia Applications Processor for Automotive Products Advance Information, Rev. 0
T
T
T
ID
cyc
wh
wl
depicts the TRACECLK timings of ETM, and
DPLL Electrical Specifications
Embedded Trace Macrocell (ETM) Electrical Specifications
Parameter
Clock period
Low pulse width
High pulse width
Parameter
Table 28. ETM TRACECLK Timing Parameters
Preliminary—Subject to Change Without Notice
Figure 6. ETM TRACECLK Timing Diagram
Table
Min.
10
Table 27. DPLL Specifications
27.
Typ.
24
Table 28
Frequency dependent
Max.
0.03
0.01
0.15
100
100
150
100
150
80
Min.
lists the timing parameters.
2
2
2 Tdck
MHz
Unit
mV
μs
μs
1
Fmodulation <50 kHz
50 kHz<Fmodulation 300 Hz
Fmodulation > 300 KHz
Fmodulation < 50 kHz
50 kHz < Fmodulation 300 Hz
Fmodulation > 300 KHz
Freescale Semiconductor
Max.
Comments
Unit
ns
ns
ns

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