MCIMX35 Motorola Semiconductor Products, MCIMX35 Datasheet - Page 80

• Manufacturer Part Number: MCIMX35
• Manufacturer: Motorola Semiconductor Products

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The DISP#_IF_CLK_PER_WR, DISP#_IF_CLK_PER_RD, HSP_CLK_PERIOD,
DISP#_IF_CLK_DOWN_WR, DISP#_IF_CLK_UP_WR, DISP#_IF_CLK_DOWN_RD,
DISP#_IF_CLK_UP_RD and DISP#_READ_EN parameters are programmed via the
DI_DISP#_TIME_CONF_1, DI_DISP#_TIME_CONF_2 and DI_HSP_CLK_PER Registers.
4.7.13.6
The IPU supports the following types of asynchronous serial interfaces:
Figure 51
DISPB_D#_CS signal and the straight polarity of the DISPB_SD_D_CLK signal.
For this interface, a bidirectional data line is used outside the device. The IPU still uses separate input and
output data lines (IPP_IND_DISPB_SD_D and IPP_DO_DISPB_SD_D). The I/O mux should provide
joining the internal data lines to the bidirectional external line according to the IPP_OBE_DISPB_SD_D
signal provided by the IPU.
Each data transfer can be preceded by an optional preamble with programmable length and contents. The
preamble is followed by read/write (RW) and address (RS) bits. The order of the these bits is
programmable. The RW bit can be disabled. The following data can consist of one word or of a whole
burst. The interface parameters are controlled by the DI_SER_DISP1_CONF and DI_SER_DISP2_CONF
Registers.
Figure 52
data lines both inside and outside the device.
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DISPB_SD_D_CLK
DISPB_D#_CS
Loopback delay Tlbd is the cumulative propagation delay of read controls and read data. It includes an IPU output delay, a
device-level output delay, board delays, a device-level input delay, an IPU input delay. This value is device specific.
DISPB_SD_D
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MCIMX35 (i.MX35) Multimedia Applications Processor for Automotive Products Advance Information, Rev. 0
3-wire (with bidirectional data line)
4-wire (with separate data input and output lines)
5-wire type 1 (with sampling RS by the serial clock)
5-wire type 2 (with sampling RS by the chip select signal)
depicts timing of the 4-wire serial interface. For this interface, there are separate input and output
depicts timing of the 3-wire serial interface. The timing images correspond to active-low
Serial Interfaces, Functional Description
1 display IF
Figure 51. 3-Wire Serial Interface Timing Diagram
clock cycle
Preliminary—Subject to Change Without Notice
Preamble
RW
RS
D7
D6
D5
Input or output data
D4
D3
Freescale Semiconductor
D2
1 display IF
clock cycle
D1
D0