MCIMX35 Motorola Semiconductor Products, MCIMX35 Datasheet - Page 35

• Manufacturer Part Number: MCIMX35
• Manufacturer: Motorola Semiconductor Products

4.7.5.2
All WEIM output control signals may be asserted and deasserted by internal clocks related to the BCLK
rising edge or falling edge according to the corresponding assertion or negation control fields. The address
always begins related to BCLK falling edge but may be ended both on rising and falling edge in muxed
mode according to control register configuration. Output data begins related to BCLK rising edge except
in muxed mode where both rising and falling edge may be used according to control register configuration.
Input data, ECB and DTACK all captured according to BCLK rising edge time.
timing of the WEIM module, and
Freescale Semiconductor
MCIMX35 (i.MX35) Multimedia Applications Processor for Automotive Products Advance Information, Rev. 0
1
2
NF16 Data Setup on READ
NF17 Data Hold on READ
The flash clock maximum frequency is 50 MHz.
Subject to DPLL jitter specification listed in
ID
Wireless External Interface Module (WEIM)
High is defined as 80% of signal value and low is defined as 20% of signal
value.
Timing for HCLK is 133 MHz and internal NFC clock (flash clock) is
approximately 33 MHz (30 ns). All timings are listed according to this NFC
clock frequency (multiples of NFC clock phases), except NF16 and NF17,
which are not NFC clock related.
Parameter
Table 30. NFC Timing Parameters
Preliminary—Subject to Change Without Notice
Table 31
Symbol
tDSR
tDHR
lists the timing parameters.
Table 27, "DPLL Specifications," on page
T = NFC Clock Cycle
NOTE
Min.
Timing
N/A
N/A
Max.
1
(continued)
2
NFC Clock
Example Timing for
Min.
10
0
T = 30 ns
Figure 12
≈
30.
33 MHz
Max.
—
—
depicts the
Unit
ns
ns
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