MCIMX35 Motorola Semiconductor Products, MCIMX35 Datasheet - Page 9

• Manufacturer Part Number: MCIMX35
• Manufacturer: Motorola Semiconductor Products

Freescale Semiconductor
Mnemonic
eSDHCv2
GPIO(3)
GPU2D
Block
I
FEC
GPT
2
(3)
C(3)
MCIMX35 (i.MX35) Multimedia Applications Processor for Automotive Products Advance Information, Rev. 0
Enhanced
secure digital
host controller
Ethernet
General
purpose I/O
modules
General
purpose timers
Graphics
processing unit
2Dv1
I
2
Block Name
C module
ARM
SDMA
ARM
ARM
ARM
ARM
Domain
Table 4. Digital and Analog Modules (continued)
Preliminary—Subject to Change Without Notice
1
peripherals
Connectivity
peripherals
Timer
peripherals
Multimedia
peripherals
ARM1136
platform
peripherals
Connectivity
Pins
Subsystem
The eSDHCv2 consists of four main modules: CE-ATA, MMC, SD
and SDIO. CE-ATA is a hard drive interface that is optimized for
embedded applications of storage. The multi-media card (MMC) is a
universal, low-cost, data storage and communication media to
applications such as electronic toys, organizers, PDAs, and smart
phones. The secure digital (SD) card is an evolution of MMC and is
specifically designed to meet the security, capacity, performance,
and environment requirements inherent in emerging audio and video
consumer electronic devices. SD cards are categorized into Memory
and I/O. A memory card enables a copyright protection mechanism
that complies with the SDMI security standard. SDIO cards provide
high-speed data I/O (such as wireless LAN via SDIO interface) with
low power consumption.
Note: CE-ATA is not available for the MCIMX351.
The Ethernet media access controller (MAC) is designed to support
both 10 and 100 Mbps Ethernet/IEEE 802.3 networks. An external
transceiver interface and transceiver function are required to
complete the interface to the media
Used for general purpose input/output to external ICs. Each GPIO
module supports 32 bits of I/O.
Each GPT is a 32-bit free-running or set-and-forget mode timer with
a programmable prescaler and compare and capture registers. A
timer counter value can be captured using an external event and can
be configured to trigger a capture event on either the leading or
trailing edges of an input pulse. When the timer is configured to
operate in set-and-forget mode, it is capable of providing precise
interrupts at regular intervals with minimal processor intervention.
The counter has output compare logic to provide the status and
interrupt at comparison. This timer can be configured to run either on
an external clock or on an internal clock.
This module accelerates OpenVG and GDI graphics.
Note: Not available for the MCIMX351.
Inter-integrated circuit (I
serial bus that provides a simple, efficient method of data exchange,
minimizing the interconnection between devices. I
applications requiring occasional communications over a short
distance among many devices. The interface operates at up to
100 kbps with maximum bus loading and timing. The I
true multiple-master bus, with arbitration and collision detection that
prevent data corruption if multiple devices attempt to control the bus
simultaneously. This feature supports complex applications with
multiprocessor control and can be used for rapid testing and
alignment of end products through external connections to an
assembly-line computer.
2
Brief Description
C) is an industry-standard, bidirectional
2
C is suitable for
2
C system is a
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