MAXQ3108 Maxim Integrated Products, MAXQ3108 Datasheet - Page 10

• Manufacturer Part Number: MAXQ3108
• Description: Dual-Core Microcontroller
• Manufacturer: Maxim Integrated Products

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Low-Power, Dual-Core Microcontroller
A 4K Word (8KB) section of memory is available to the
DSPCore as code memory. When the DSPCore is dis-
abled (as it is immediately following a reset event) that
block of memory appears in the UserCore data memory
map at location 0x1000. Thus, a typical startup
sequence to operate both cores might include:
1) Low-level initialization of the UserCore.
2) Copy DSP code from program flash to DSPCore
3) Enable DSPCore.
4) Poll mailbox registers to verify that DSPCore is cor-
For more information, see the Dual-Core Interfaces
section.
The MAXQ family of microcontrollers uses a bank of
registers to access memory and peripherals and to per-
form basic CPU activities. These registers are orga-
nized into as many as 16 register modules, each of
which can have as many as 32 registers, giving a sys-
tem maximum of 512 registers. The registers are divid-
ed into two sections: system registers (modules 7 to 15)
and peripheral registers (modules 0 to 5).
Since the MAXQ3108 contains two MAXQ core proces-
sors, each has a set of system registers and a set of
peripheral registers.
The MAXQ3108 UserCore implements the standard set
of system registers as described in the MAXQ Family
User’s Guide . The exceptions are listed below:
• In the IMR register, bit IM5 is not implemented since
Table 1. UserCore Peripheral Registers
10
REGISTER
AD0LSB
there is no module 5 implemented in the MAXQ3108.
SRSP0
SRSP1
code RAM at 0x1000.
rectly running.
AD0
AD1
AD2
AD3
AD4
AD5
______________________________________________________________________________________
MOD:
REG
0:0
0:1
0:2
0:3
0:4
0:5
0:6
0:7
0:8
15
14
13
DSP Program RAM
System Registers
12
Registers
11
10
Slave Response Register 1
9
ADC0 Output Register
ADC1 Output Register
ADC2 Output Register
ADC3 Output Register
ADC4 Output Register
ADC5 Output Register
• In the SC register, bits CDA1 and UPM are not imple-
• In the IIR register, bit II5 is not implemented since
• In the CKCN register, bits XT/RC, RGSL, and
The MAXQ3108 DSPCore system register complement
is identical to that found in the UserCore, with these
exceptions:
• In the IMR register, only IM0 is implemented.
• The system control (SC) register is not implemented.
• In the IIR register, only the II0 bit is implemented.
• The WDCN register is not implemented because
• In the CKCN register, the STOP, RGSL, and SWB bits
The MAXQ3108 UserCore exposes its peripheral com-
plement in five modules numbered 0 to 4. Table 1
describes the functions associated with the peripheral
registers, and Table 2 shows the default values of these
registers.
mented since the size of the memory in the device
does not require their implementation.
there is no module 5 implemented in the MAXQ3108.
RGMD are not implemented. Instead, bits 5 and 6
are FLLMD and FLLSL, respectively. These bits
support the frequency-locked loop (FLL) that forms
a core part of the MAXQ3108 clocking scheme.
More information is given in the Clock section.
there is no watchdog timer in the DSPCore.
Watchdog functionality can be implemented in the
UserCore by determining if the DSPCore is respond-
ing to messages.
are not implemented because the corresponding
functions do not exist in the DSPCore. The FLLMD
and FLLSL bits are not implemented because a com-
mon clock block is shared with the UserCore, and
the control bits here would be redundant.
8
BIT
7
Peripheral Registers—UserCore
6
RSPSDV
ADC0 Output Register LSB
5
REQE
4
3
2
RSPST
1
0