MAXQ3108 Maxim Integrated Products, MAXQ3108 Datasheet - Page 40

• Manufacturer Part Number: MAXQ3108
• Description: Dual-Core Microcontroller
• Manufacturer: Maxim Integrated Products

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Low-Power, Dual-Core Microcontroller
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MB (02h, 03h)
Initialization:
Read/Write Access:
MB.[15:0]:
MC2 (03h, 03h)
Initialization:
Read/Write Access:
MC2.[15:0]:
MC1 (04h, 03h)
Initialization:
Read/Write Access:
MC1.[15:0]:
MC0 (05h, 03h)
Initialization:
Read/Write Access:
MC0.[15:0]:
SPIB (07h, 03h)
Initialization:
Read/Write Access:
SPIB.[15:0]:
MC1R (08h, 03h)
Initialization:
Read/Write Access:
MC1R.[15:0]:
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Multiplier Operand B Register
This register is cleared to 0000h on all forms of reset.
Unrestricted read/write.
Multiplier Operand B Bit 15:0. This operand B register is used by the user software to load a 16-bit
value for a multiplier operation. Loading of the MA and MB registers initiates a selected multiplier
operation, dependent on the setting of the MMAC bit. The data type is determined by the SUS bit.
The result is stored to the MC register.
Multiplier Accumulate Register 2
This register is cleared to 0000h on all forms of reset.
Unrestricted read/write.
Multiplier Accumulate Register 2 Bit 15:0. The MC2 register represents the two most significant
bytes of the accumulator register. The 48-bit accumulator is formed by MC2, MC1, and MC0. This
register is used in multiply-accumulate operation. For a signed operation, the most significant bit
of this register is the signed bit.
Multiplier Accumulate Register 1
This register is cleared to 0000h on all forms of reset.
Unrestricted read/write.
Multiplier Accumulate Register 1 Bit 15:0. The MC1 register represents bytes 3 and 2 of the
accumulator register. The 48-bit accumulator is formed by MC2, MC1, and MC0.
Multiplier Accumulate Register 0
This register is cleared to 0000h on all forms of reset.
Unrestricted read/write.
Multiplier Accumulate Register 0 Bit 15:0. The MC0 register represents the two least significant
bytes of the accumulator register. The 48-bit accumulator is formed by MC2, MC1, and MC0.
SPI Data Buffer (16-Bit Register)
This buffer is cleared to 0000h on all forms of reset.
Unrestricted read, write is allowed outside of a transfer cycle; when the STBY bit is set, write is
blocked and causes write collision error.
SPI Data Buffer Bits 15:0. Data for SPI is read from or written to this location. The serial transmit
and receive buffers are separate but both are addressed at this location.
Multiplier Read Register 1
This register is cleared to 0000h on all forms of reset.
Unrestricted read-only.
Multiplier Read Register 1 Bit 15:0. During multiplication, the MC1R register represents bytes 3
and 2 result from the last operation when MCW bit is 1 or the last operation is either multiply-only
or multiply-negate. When MCW bit is 0 and the last operation is either multiply-accumulate or
multiply-subtract, the contents of this register may or may not agree with the contents of MC1 due
to the combinatorial nature of the adder. The contents of this register remain until a SFR content
related to the multiplier has been changed.
Special Function Register Bit Descriptions (continued)