MAXQ3108 Maxim Integrated Products, MAXQ3108 Datasheet - Page 54

• Manufacturer Part Number: MAXQ3108
• Description: Dual-Core Microcontroller
• Manufacturer: Maxim Integrated Products

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Low-Power, Dual-Core Microcontroller
Since PMM is incompatible with any operation that
requires a precise clock (for example, baud-rate gener-
ation), attempts to set the PMME bit while such opera-
tions are active will fail.
Note that when switchback is enabled in PMM2 mode,
the high-frequency clock (the FLL) continues to run to
support the switchback operation.
The stop-mode bit is only implemented for the
MAXQ3108 UserCore (the DSPCore does not support
stop mode). Stop mode disables all circuits within the
processor except the 32,768Hz crystal amplifier and
any circuitry that is directly clocked by the 32,768Hz
oscillator. All other on-chip clocks, timers, and serial
port communication are stopped, and no processing is
possible. Once in stop mode, the device is in a static
state, its power consumption primarily dominated by
leakage current.
Stop mode is invoked by setting the STOP bit to logic 1.
The processor enters the stop mode on the instruction
that sets the STOP bit. Entering the stop mode does not
affect the setting of the clock control bits, allowing the
system to return to its original operating frequency after
stop mode is exited. If reset ends stop mode, the clock
generation logic is returned to its default condition.
The processor can exit stop mode through the following:
• By using any of the external interrupts that are
• By external reset through the RST pin.
• By the time-of-day alarm or subsecond alarm from
• By the I
• By the SVM interrrupt if enabled (SVMIE = 1).
When stop mode is exited, the processor resumes its
normal execution. When the UserCore invokes stop
mode, the DSPCore is disabled in hardware. This
means that on any exit from stop mode, the DSP must
be reconfigured and reenabled if this functionality is
desired. This also means that user code may need to
handle an interrupt source differently depending on
whether it occurs while both CPUs are running or
whether it removes stop mode.
Idle mode is only implemented for the MAXQ3108
DSPCore (not the UserCore). Idle mode suspends the
processor by holding the instruction pointer (IP) in a
static state. No instructions are fetched and no pro-
cessing occurs. Setting the IDLE bit to logic 1 invokes
54
enabled.
the RTC.
I2CEN = 1).
______________________________________________________________________________________
2
C start interrupt if enabled (I2CSRIE = 1 and
Stop Mode
Idle Mode
the idle mode. The instruction that executes this step is
the last instruction prior to freezing the program
counter. Once in idle mode, all resources are pre-
served and clocks remain active to enabled peripherals
so the processor can exit the idle state using any of the
interrupt sources that are enabled. Note that the only
interrupts associated with the DSPCore (i.e., those that
can remove idle mode) are master request (from
UserCore), and ADC output buffer interrupts. The IDLE
bit is cleared automatically once the idle state is exited;
allowing the processor to execute the instruction at the
corresponding interrupt vector address. Upon returning
from the interrupt vector, the processor executes the
instruction that immediately follows the one that set the
IDLE bit. Resetting the processor also removes the idle
mode. Reset places the processor in a reset state and
clears the IDLE bit. The DSPCore reset state could
result from a global system reset or from clearing of the
ENDSP bit by the UserCore.
The MAXQ3108 has four ways of entering a reset state:
• Power-on reset
• Watchdog timer reset
• External reset
• Internal system reset
Regardless of the reset source, the state of the
MAXQ3108 is the same while in reset. When in reset,
the oscillator/FLL oscillator is running, but no program
execution is allowed. When the reset source is external,
the user must remove the reset stimulus. When power is
applied to the device, the power-on delay removes the
stimulus automatically.
The MAXQ3108 incorporates an internal voltage refer-
ence and comparator in order to monitor V
the device in reset if the supply is out of tolerance.
Once V
MAXQ3108 generates a power-on reset, starts the inter-
nal FLL, and counts 65,536 FLL cycles (POR delay)
before program execution begins at location 8000h.
The power monitor invokes the reset state whenever the
supply drops below the POR threshold. This reset con-
dition remains until the supply voltage is above the min-
imum operating voltage level. When power returns
above the reset threshold, a full power-on reset is per-
formed. Thus, a brownout that causes V
below the minimum voltage appears the same as a
power-up.
The MAXQ3108 provides a brownout detect/reset func-
tion. Brownout detection is always enabled during
Power-On Reset/Brownout Reset Generation
DD
has risen above the threshold, the
DD
DD
and hold
to drop
Reset