MAXQ3108 Maxim Integrated Products, MAXQ3108 Datasheet - Page 57

• Manufacturer Part Number: MAXQ3108
• Description: Dual-Core Microcontroller
• Manufacturer: Maxim Integrated Products

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The other party, the slave, recognizes its address and
responds by accepting data or delivering data. A data
transfer sequence can be grouped into the following
stages:
• START: The master generates the START condition
• Address: The master transmits the address of the
• Address Acknowledge: The slave with the matching
• Data: The transmitter sends data to the receiver. The
• Data Acknowledge: The receiver acknowledges to
• STOP: The master concludes the transfer by send-
The MAXQ3108 I
manage I
• I2CBUF: The buffer register through which all out-
• I2CCK: The I
• I2CCN: The control register manages the I
• I2CST: The status register contains bits that reflect
• I2CIE: The interrupt enable register is used to man-
• I2CTO: The timeout register defines how long a slave
• I2CSLA: Establishes the slave address for the I
(S) by pulling SDA low (high-to-low transition) while
holding SCL high.
slave device, together with the direction of data
transfer (R/W).
address responds to the master by holding SDA low
during the 9th clock SCL high (A).
number of bytes of data is unlimited. However, each
data byte must be followed by a data-acknowledge
bit (A).
the transmitter by sending the acknowledge bit (A). If
the master is the receiver and the data just received
is the last byte expected, the master leaves SDA
high to signal to the slave transmitter that the last
byte of expected data is transmitted. The slave trans-
mitter then releases SDA after the 9th clock so that
the master can generate a STOP or START condition.
ing the STOP condition (P) by causing a low-to-high
transition on SDA while SCL is high. The I
now idle.
bound data is written, and through which all inbound
data is received.
low periods for the SCL signal.
eral during configuration and operation.
the condition of the I
quently during I
age interrupt sources within the I
can extend the I
declares a timeout.
peripheral.
2
C bus communication:
2
C clock register defines the high and
2
2
______________________________________________________________________________________
C peripheral uses seven registers to
C operation.
2
C clock before the peripheral
2
C peripheral. It is consulted fre-
Low-Power, Dual-Core Microcontroller
2
C peripheral.
2
2
C periph-
C bus is
2
C
I
to Slave
1) Set the I2CEN and I2CMST bits in the I2CCN regis-
2) Set the I2CSTART bit in the I2CCN register. This
3) Load the command byte into I2CBUF. The com-
4) Monitor the I2CTXI flag in the I2CST register. When
5) Load the first data byte into I2CBUF.
6) Monitor the I2CTXI flag in the I2CST register. When
7) Load the second data byte into I2CBUF.
8) Monitor the I2CTXI flag in the I2CST register. When
9) Set the I2CSTOP bit in the I2CCN register. This
I
Bytes from Slave
1) Set the I2CEN and I2CMST bits in the I2CCN regis-
2) Set the I2CSTART bit in the I2CCN register. This
2
2
C Use Scenario: MAXQ3108 Master Sends 2 Bytes
C Use Scenario: MAXQ3108 Master Receives 2
ter. This enables the I
the MAXQ3108 as master.
causes the MAXQ3108 to send the START
sequence. When the START condition has been
sent (and both SDA and SCL are low), the
I2CSTART bit is cleared. Note that the I2CSRI bit is
set in the I2CST register as well. That is because
the I
mand byte consists of the slave address and the
R/W bit. For this example, assume we wish to write
to slave address 0x30. The byte to be loaded in this
case is 0x60: the address shifted up by one posi-
tion and bit 0 (the R/W bit) set to 0.
set, the I
command byte and has received an ACK or a NAK
from the remote device. Check the I2CNACKI flag in
the I2CST register to determine if an ACK or a NAK
was received. If set, the command was not acknowl-
edged. Clear these bits after they are tested.
set, the I
data byte. Check the I2CNACKI flag to ensure that
the slave has received the byte. Clear both these
bits.
set, the I
data byte. Check the I2CNACKI flag to ensure that
the slave has received the byte. Clear both these
bits.
causes the MAXQ3108 to send the STOP
sequence. When this bit returns to 0, the STOP
sequence has been sent and the I
ter. This enables the I
the MAXQ3108 as master.
causes the MAXQ3108 to send the START
sequence. When the START condition has been
2
C peripheral sees its own START condition.
2
2
2
C peripheral has finished sending the
C peripheral has finished sending the
C peripheral has finished sending the
2
2
C peripheral and establishes
C peripheral and establishes
2
C bus is idle.
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