AD1846 Analog Devices, AD1846 Datasheet - Page 11

• Manufacturer Part Number: AD1846
• Description: Low Cost Parallel-port 16-bit Soundport Stereo Codec
• Manufacturer: Analog Devices

REV. A
CONTROL REGISTERS
Control Register Architecture
The AD1846 SoundPort Stereo Codec accepts both data and
control information through its byte-wide parallel port. Indirect
addressing minimizes the number of external pins required to
access all 21 of its byte-wide internal registers. Only two exter-
nal address pins, ADR1:0, are required to accomplish all data
and control transfers. These pins select one of five direct regis-
ters. (ADR1:0 = 3 addresses two registers, depending on
whether the transfer is a playback or a capture.)
A write to or a read from the Indexed Data Register will access
the indirect register which is indexed by the value most recently
written to the Index Address Register. The Status Register and
the PIO Data Register are always accessible directly, without in-
dexing. The 16 indirect registers are indexed in Figure 5.
Note that the only sticky bit in any of the AD1846 control registers is the interrupt (INT) bit. All other bits change with every
sample period.
Direct Registers:
Indirect Registers:
ADR1:0
ADR1:0
IXA3:0
0
1
2
3
10
11
12
13
14
15
0
1
2
3
3
0
1
2
3
4
5
6
7
8
9
Figure 4. Direct Register Map
Index Address Register
Indexed Data Register
Status Register
PIO Data Registers
XCTL1
Register Name
Data 7
Data 7
DMA5
LMX1
RMX1
LMX2
RMX2
IXD7
CU/L
LDM
RDM
CPIO
INIT
LSS1
RSS1
CD7
PD7
COR
UB7
LB7
res
res
XCTL0
Data 6
Data 6
DMA4
IXD6
PPIO
MCE
CL/R
LSS0
RSS0
FMT
CD6
PD6
PUR
UB6
LB6
res
res
res
res
res
res
res
Data 5
Data 5
LMGE
RMGE
DMA3
Figure 6. Register Summary
CRDY
LDA5
RDA5
IXD5
TRD
CD5
PD5
UB5
LB5
C/L
ACI
res
res
res
res
res
res
res
LX1A4
LX2A4
RX1A4
RX2A4
–11–
Data 4
Data 4
DMA2
SOUR
LDA4
RDA4
IXD4
CD4
PD4
DRS
UB4
LB4
S/M
res
res
res
res
res
res
A detailed map of all direct and indirect register contents is
summarized for reference as follows:
LX1A3
RX1A3
LX2A3
RX2A3
Data 3
Data 3
DMA1
LDA3
RDA3
ACAL
ORR1
IXD3
PU/L
LIG3
RIG3
CFS2
IXA3
CD3
PD3
UB3
LB3
ID3
res
Index
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
Figure 5. Indirect Register Map
LX1A2
RX1A2
LX2A2
RX2A2
Data 2
Data 2
DMA0
LDA2
RDA2
ORR0
IXD2
LIG2
RIG2
CFS1
IXA2
PL/R
CD2
PD2
SDC
UB2
Left Input Control
Right Input Control
Left Aux #1 Input Control
Right Aux #1 Input Control
Left Aux #2 Input Control
Right Aux #2 Input Control
Left Output Control
Right Output Control
Clock and Data Format
Interface Configuration
Pin Control
Test and Initialization
Miscellaneous Information
Digital Mix
Upper Base Count
Lower Base Count
LB2
ID2
res
Register Name
LX1A1
RX1A1
LX2A1
RX2A1
Data 1
Data 1
PRDY
LDA1
RDA1
ORL1
IXD1
LIG1
RIG1
CFS0
IXA1
CEN
CD1
PD1
UB1
IEN
LB1
ID1
res
RX1A0
RX2A0
LX1A0
LX2A0
AD1846
Data 0
Data 0
LDA0
RDA0
ORL0
IXD0
LIG0
RIG0
DME
IXA0
CD0
PD0
PEN
UB0
INT
CSS
LB0
ID0
res