AD1846 Analog Devices, AD1846 Datasheet - Page 13

• Manufacturer Part Number: AD1846
• Description: Low Cost Parallel-port 16-bit Soundport Stereo Codec
• Manufacturer: Analog Devices

REV. A
INT
PRDY
PL/R
PU/L
SOUR
CRDY
CL/R
CU/L
The PRDY, CRDY, and INT bits of this status register can change asynchronously to host accesses. The host may access this regis-
ter while the bits are transitioning. The host read may return a zero value just as these bits are changing, for example. A “1” value
would not be read until the next host access.
This registers’s initial state after reset is “1100 1100.”
Status Register (ADR1:0 = 2)
ADR1:0
2
Interrupt Status. This sticky bit (the only one) indicates the status of the interrupt logic of the AD1846. This bit is cleared
by any host write of any value to this register. The IEN bit of the Pin Control Register determines whether the state of this
bit is reflected on the INT pin of the AD1846. The only interrupt condition supported by the AD1846 is generated by the
underflow of the DMA Current Count Register.
0
1
Playback Data Register Ready. The PIO Playback Data Register is ready for more data. This bit should only be used when
direct programmed I/O data transfers are desired. This bit is read only.
0
1
Playback Left/Right Sample. This bit indicates whether the PIO playback data needed is for the right channel DAC or left
channel DAC. This bit is read only.
0
1
Playback Upper/Lower Byte. This bit indicates whether the PIO playback data needed is for the upper or lower byte of the
channel. This bit is read only.
0
1
Sample Over/Underrun. This bit indicates that the most recent sample was not serviced in time and therefore either a cap-
ture overrun (COR) or playback underrun (PUR) has occurred. The bit indicates an overrun for ADC capture and an
underrun for DAC playback. If both capture and playback are enabled, the source which set this bit can be determined by
reading COR and PUR. This bit changes on a sample-by-sample basis. This bit is read only.
Capture Data Ready. The PIO Capture Data Register contains data ready for reading by the host. This bit should only be
used when direct programmed I/O data transfers are desired. This bit is read only.
0
1
Capture Left/Right Sample. This bit indicates whether the PIO capture data waiting is for the right channel ADC or left
channel ADC. This bit is read only.
0
1
Capture Upper/Lower Byte. This bit indicates whether the PIO capture data ready is for the upper or lower byte of the
channel. This bit is read only.
0
1
Interrupt pin inactive
Interrupt pin active
DAC data is still valid. Do not overwrite.
DAC data is stale. Ready for next host data write value.
Right channel needed
Left channel or mono
Lower byte needed
Upper byte needed or any 8-bit mode
ADC data is stale. Do not reread the information.
ADC data is fresh. Ready for next host data read.
Right channel
Left channel or mono
Lower byte ready
Upper byte ready or any 8-bit mode
Data 7
CU/L
Data 6
CL/R
Data 5
CRDY
Data 4
SOUR
–13–
Data 3
PU/L
Data 2
PL/R
Data 1
PRDY
AD1846
Data 0
INT