AD1846 Analog Devices, AD1846 Datasheet - Page 21

• Manufacturer Part Number: AD1846
• Description: Low Cost Parallel-port 16-bit Soundport Stereo Codec
• Manufacturer: Analog Devices

REV. A
DATA AND CONTROL TRANSFERS
The AD1846 SoundPort Stereo Codec supports a DMA re-
quest/grant architecture for transferring data with the host com-
puter bus. One or two DMA channels can be supported.
Programmed I/O (PIO) mode is also supported for control reg-
ister accesses and for applications lacking DMA control. PIO
transfers can be made on one channel while the other is per-
forming DMA. Transfers to and from the AD1846 SoundPort
Codec are asynchronous relative to the internal data conversion
clock. Transfers are buffered, but the AD1846 supports no in-
ternal FIFOs. The host is responsible for providing playback
data before the next digital-to-analog conversion and removing
capture data before the next analog-to-digital conversion.
Data Ordering
The number of byte-wide transfers required depends on the
data format selected. The AD1846 is designed for “little
endian” formats in which the least significant byte (i.e., occupy-
ing the lowest memory address) gets transferred first. So 16-bit
data transfers require first transferring the least significant bits
7:0 and then transferring the most significant bits 15:8, where
bit 15 is the most significant bit in the word.
In addition, left channel data is always transferred before right
channel data with the AD1846. The following figures should
make these requirements clear.
SAMPLE 6
SAMPLE 3
SAMPLE 6
SAMPLE 3
Figure 10. 16-Bit Stereo Data Stream Sequencing
Figure 9. 16-Bit Mono Data Stream Sequencing
Figure 8. 8-Bit Stereo Data Stream Sequencing
Figure 7. 8-Bit Mono Data Stream Sequencing
BYTE 4
BYTE 4
MONO
RIGHT
BYTES 3 & 4
BYTES 3 & 4
SAMPLE 5
SAMPLE 3
SAMPLE 5
SAMPLE 3
MONO
RIGHT
BYTE 3
BYTE 3
MONO
LEFT
SAMPLE 4
SAMPLE 2
SAMPLE 2
SAMPLE 4
SAMPLE 3
SAMPLE 2
SAMPLE 3
SAMPLE 2
BYTE 2
BYTE 2
MONO
RIGHT
BYTES 1 & 2
BYTES 1 & 2
SAMPLE 2
SAMPLE 1
SAMPLE 1
SAMPLE 2
MONO
LEFT
BYTE 1
BYTE 1
MONO
LEFT
SAMPLE 1
SAMPLE 1
SAMPLE 1
SAMPLE 1
TIME
TIME
TIME
TIME
–21–
Control and Programmed I/O (PIO) Transfers
This simpler mode of transfers is used both for control register
accesses and programmed I/O. The 21 control and PIO data
registers cannot he accessed via DMA transfers. Playback PIO is
activated when both Playback Enable (PEN) is set and Playback
PIO (PPIO) is set. Capture PIO is activated when both Capture
Enable (CEN) is set and Capture PIO (CPIO) is set. See Fig-
ures 11 and 12 for the detailed timing of the control register/
PIO transfers. The RD and WR signals are used to define the
actual read and write cycles, respectively. The host holds CS
LO during these transfers. The DMA Capture Data Acknowl-
edge (CDAK) and Playback Data Acknowledge (PDAK) must
be held inactive, i.e., HI.
For read/capture cycles, the AD1846 will place data on the
DATA7:0 lines while the host is asserting the read strobe, RD,
by holding it LO. For write/playback, the host must place data
on the DATA7:0 pins while strobing the WR signal LO. The
AD1846 latches the write/playback data on the rising edge of
the WR strobe.
When using PIO data transfers, the Status Register must be
polled to determine when data should be transferred. Note that
the ADC capture data will be ready (CRDY HI) from the previ-
ous sample period shortly before the DAC playback data is
ready (PRDY HI) for the next sample period. The user should
not wait for both ADCs and DACs to become ready before initi-
ating data transfers. Instead, as soon as capture data is ready, it
should be read; as soon as the DACs are ready, playback data
should he written.
Values written to the XCTL1:0 bits in the Pin Control Register
(IA3:0 = 10) will be reflected in the state of the XCTL1:0 exter-
nal output pins. This feature allows a simple method for signal-
ing or software control of external logic. Changes in state of the
external XCTL pins will occur within one sample period. Be-
cause their change is referenced to the internal sample clock, no
useful timing diagram can be constructed.
OUTPUTS
OUTPUTS
RD INPUT
OUTPUTS
CS INPUT
DATA7:0
DBEN &
ADR1:0
INPUTS
CDRQ /
DBDIR
INPUT
PDRQ
CDAK
Figure 11. Control Register/PIO Read Cycle
t
CSSU
t
SUDK1
t
ADSU
t
RDDV
t
t
DBDL
STW
t
CSHD
AD1846
t
SUDK2
t
DHD1
t
ADHD