AD1846 Analog Devices, AD1846 Datasheet - Page 18

• Manufacturer Part Number: AD1846
• Description: Low Cost Parallel-port 16-bit Soundport Stereo Codec
• Manufacturer: Analog Devices

AD1846
The contents of the Interface Configuration Register cannot be changed except when the AD1846 is in Mode Change Enable (MCE) state.
Write attempts to this register when the AD1846 is not in the MCE state will not be successful. PEN and CEN are exceptions; these bits may al-
ways be written.
PEN
CEN
SDC
ACAL
res
PPIO
CPIO
This register’s initial state after reset is “00xx 1000.”
res
IEN
XCTL1:0 External Control. The state of these independent bits is reflected on the respective XCTL1:0 pins of the AD1846.
This register’s initial state after reset is “00xx xx0x.”
Interface Configuration Register (IXA3:0 = 9)
Pin Control Register (IXA3:0 = 10)
IXA3:0
IXA3:0
10
9
Playback Enable. This bit will enable the playback of data in the format selected. The AD1846 will generate PDRQ and
respond to PDAK signals when this bit is enabled and PPIO = 0. If PPIO = 1, this bit enables Programmed I/O (PIO)
playback mode. PEN may be set and reset without setting the MCE bit.
0
1
Capture Enable. This bit will enable the capture of data in the format selected. The AD1846 will generate CDRQ and re-
spond to CDAK signals when this bit is enabled and CPIO = 0. If CPIO = 1, this bit enables PIO capture mode. CEN
may be set and reset without setting the MCE bit.
0
1
Single DMA Channel. This bit will force both capture and playback DMA requests to occur on the Playback DMA chan-
nel. The Capture DMA CDRQ pin will be LO. This bit will allow the AD1846 to be used with only one DMA channel.
Simultaneous capture and playback cannot occur in this mode. Should both capture and playback be enabled
(CEN = PEN = 1) in the mode, only playback will occur. See “Data and Control Transfers” for further explanation.
0
1
Autocalibrate Enable. This bit determines whether the AD1846 performs an autocalibrate whenever the PWRDWN pin is
deasserted or from the Mode Change Enable (MCE) bit being reset. ACAL is normally set. See “Autocalibration” below
for a description of a complete autocalibration sequence.
0
1
Reserved for future expansion. Always write zeros to these bits.
Playback PIO Enable. This bit determines whether the playback data is transferred via DMA or PIO.
0
1
Capture PIO Enable. This bit determines whether the capture data is transferred via DMA or PIO.
0
1
Reserved for future expansion. Always write zeros to these bits.
Interrupt Enable. This bit enables the interrupt pin. The Interrupt Pin will go active HI when the number of samples pro-
grammed in the Base Count Register is reached.
0
1
0
1
Playback disabled (PDRQ and PIO Playback Data Register inactive)
Playback enabled
Capture disabled (CDRQ and PIO Capture Data Register inactive)
Capture enabled
Dual DMA channel mode
Single DMA channel mode
No autocalibration
Autocalibration after power down/reset or mode change
DMA transfers only
PIO transfers only
DMA transfers only
PIO transfers only
Interrupt disabled
Interrupt enabled
TTL Logic LO on XCTL1:0 pins
TTL Logic HI on XCTL1:0 pins
XCTL1
Data 7
Data 7
CPIO
XCTL0
Data 6
Data 6
PPIO
Data 5
Data 5
res
res
Data 4
Data 4
–18–
res
res
Data 3
Data 3
ACAL
res
Data 2
Data 2
SDC
res
Data 1
Data 1
CEN
IEN
Data 0
Data 0
PEN
res
REV. A