KSZ8041 Hynix Semiconductor, KSZ8041 Datasheet
KSZ8041
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KSZ8041 Summary of contents
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... DDR SDRAM This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.04 /Jul. 2006 HY5DU281622FTP 1 ...
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Revision History Revision No. 0.01 First version for internal review 0.02 State Diagram modified 0.03 Defined : IDD value 0.04 Insert : 250MHz CL4 Product Rev. 0.04 /Jul. 2006 HY5DU281622FT(P) Series History Draft Date Remark Feb. 2006 Apr. 2006 Apr. ...
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DESCRIPTION The HY5DU281622FT( 134,217,728-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. This Hynix 128Mb DDR SDRAMs offer fully synchronous operations referenced to both rising ...
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PIN CONFIGURATION DD V DQ0 DDQ V DQ1 DQ2 SSQ V DQ3 DQ4 DDQ V DQ5 DQ6 SSQ V DQ7 NC DDQ V LDQS LDM /WE /CAS /RAS /CS NC BA0 BA1 A10/ ...
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PIN DESCRIPTION PIN TYPE Clock: CK and /CK are differential clock inputs. All address and control input signals are CK, /CK Input sampled on the crossing of the positive edge of CK and negative edge of /CK. Output (read) data ...
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Functinal Block Diagram (8M x16) 4Banks x 2Mbit x 16I/O Double Data Rate Syncronous DRAM CLK /CLK CKE /CS Command /RAS Decoder /CAS /WE Register LDM UDM A0 A1 Address Buffer max A BA0 BA1 Rev. 0.04 /Jul. 2006 Write ...
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SIMPLIFIED COMMAND TRUTH TABLE Command CKEn-1 Extended Mode Register Set Mode Register Set Device Deselect No Operation Bank Active Read Read with Autoprecharge Write Write with Autoprecharge Precharge All Banks Precharge selected Bank Read Burst Stop Auto Refresh Entry Self ...
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Note : 1. UDM, LDM states are Don’t Care. Refer to below Write Mask Truth Table.(note Code(Operand Code) consists of A0~A11 and BA0~BA1 used for Mode Register setting during Extended MRS or MRS. Before entering Mode Register ...
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SIMPLIFIED STATE DIAGRAM MODE REGISTER SET POWER DOWN READ WRITE READAP WRITE WRITEAP PRE(PALL) Rev. 0.04 /Jul. 2006 MRS SREF IDLE SREX PDEN PDEX AREF ACT POWER DOWN PDEN PDEX BANK ACTIVE WRITE READ WITH WITH AUTOPRE- AUTOPRE- CHARGE CHARGE ...
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POWER-UP SEQUENCE AND DEVICE INITIALIZATION DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Power must first be applied to V (and to the system VTT). ...
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Power-Up Sequence VDD VDDQ tVTD VTT VREF /CLK CLK tIS tIH LVCMOS Low Level CKE CMD NOP DM ADDR A10 BA0, BA1 DQS DQ'S T=200usec Power UP VDD and CK stable Rev. 0.04 /Jul. 2006 PRE EMRS MRS NOP CODE ...
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MODE REGISTER SET (MRS) The mode register is used to store the various operating modes such as /CAS latency, addressing mode, burst length, burst type, test mode, DLL reset. The mode register is programed via MRS command. This command is ...
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BURST DEFINITION Burst Length Starting Address (A2,A1,A0 BURST LENGTH & TYPE Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable. The burst length determines the maximum number of column ...
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CAS LATENCY The Read latency or CAS latency is the delay in clock cycles between the registration of a Read command and the availability of the first burst of output data. The latency can be programmed 2 or 2.5 clocks ...
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EXTENDED MODE REGISTER SET (EMRS) The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional func- tions include DLL enable/disable, output driver strength selection(optional). These functions are controlled via the bits shown below. The Extended ...
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ABSOLUTE MAXIMUM RATINGS Parameter Operating Temperature (Ambient) Storage Temperature Voltage on V relative Voltage on V relative to V DDQ SS Voltage on inputs relative Voltage on I/O pins relative to V Output ...
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The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire temper- ature and voltage range, for device drain to source voltages from 0.25V to 1.0V. For a given ...
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DC CHARACTERISTICS II (2M x4Bank x16I/O) 8Mx16 Parameter Symbol One bank; Active - Precharge ; t Operating DD0 Current per clock cycle; address and control inputs changing once per clock cycle One bank; Active - ...
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Parameter Symbol Burst=2; Reads; Continuous burst; One bank active; Operating I Address and control inputs changing once per clock DD4R Current cycle Burst=2; Writes; Continuous burst; One bank active; Operating Address and control inputs changing once per clock ...
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DC CHARACTERISTICS II (2M x4Bank x16I/O) 8Mx16 Parameter Symbol One bank; Active - Precharge ; t Operating DD0 Current per clock cycle; address and control inputs changing once per clock cycle One bank; Active - ...
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Parameter Symbol Burst=2; Reads; Continuous burst; One bank active; Operating I Address and control inputs changing once per clock DD4R Current cycle; t Burst=2; Writes; Continuous burst; One bank active; Operating Address and control inputs changing once per clock I ...
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DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7 IDD1 : Operating current: One bank operation o 1. Typical Case : VDD = 2.6V, T= Worst Case : VDD = 2.7V Only one bank ...
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AC OPERATING CONDITIONS Parameter Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals Input Differential Voltage, CK and /CK inputs Input Crossing Point Voltage, CK and /CK inputs Note: ...
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AC CHARACTERISTICS Parameter Row Cycle Time Auto Refresh Row Cycle Time Row Active Time Active to Read with Auto Precharge Delay Row Address to Column Address Delay Row Active to Row Active Delay Column Address to Column Address Delay Row ...
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Parameter Row Cycle Time Auto Refresh Row Cycle Time Row Active Time Active to Read with Auto Precharge Delay Row Address to Column Address Delay Row Active to Row Active Delay Column Address to Column Address Delay Row Precharge Time ...
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Parameter Data-out high-impedance window from CK,/CK Data-out low-impedance window from CK, /CK Input Setup Time (fast slew rate) 14,16-18 Input Hold Time (fast slew rate) Input Setup Time (slow slew rate) Input Hold Time (slow slew rate) 17 Input Pulse ...
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Parameter Data-out high-impedance window from CK Data-out low-impedance window from CK Input Setup Time (fast slew rate) 14,16-18 Input Hold Time (fast slew rate) Input Setup Time (slow slew rate) Input Hold Time (slow slew ...
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... System designers will use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers will correlate to their production test conditions (generally a coaxial transmission line terminated at the tester elec- tronics) ...
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The pulse duration distortion of on-chip clock circuits; and ...
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SYSTEM CHARACTERISTICS CONDITIONS for DDR SDRAMS The following tables are described specification parameters that required in systems using DDR devices to ensure proper performannce. These characteristics are for system simulation purposes and are guaranteed by design. Input Slew Rate for ...
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Note: 1. Pullup slew rate is characterized under the test conditions as shown in below Figure. Output (VOUT) 50 VSSQ 2. Pulldown slew rate is measured under the test conditions shown in below Figure. VDDQ Output (VOUT) 3. Pullup slew ...
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CAPACITANCE o (T =25 C, f=100MHz) A Parameter Input Clock Capacitance Delta Input Clock Capacitance Input Capacitance Delta Input Capacitance Input / Output Capacitance Delta Input / Output Capacitance Note: 1. VDD = min. to max., VDDQ = 2.3V to ...
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PACKAGE INFORMATION 400mil 66pin Thin Small Outline Package 22.33 (0.879) 22.12 (0.871) 0.65 (0.0256) BSC 1.194 (0.0470) 0.991 (0.0390) Rev. 0.04 /Jul. 2006 BASE PLANE 0.35 (0.0138) 0.25 (0.0098) SEATING PLANE HY5DU281622FT(P) Series Unit : mm(Inch) 11.94 (0.470) 11.79 (0.462) ...