KSZ8041 Hynix Semiconductor, KSZ8041 Datasheet - Page 8

• Manufacturer Part Number: KSZ8041
• Manufacturer: Hynix Semiconductor

Rev. 0.04 /Jul. 2006
Note :
1. UDM, LDM states are Don’t Care. Refer to below Write Mask Truth Table.(note 6)
2. OP Code(Operand Code) consists of A0~A11 and BA0~BA1 used for Mode Register setting during Extended MRS or MRS. Before
3. If a Read with Auto-precharge command is detected by memory component in CK(n), then there will be no command presented
4. If a Write with Auto-precharge command is detected by memory component in CK(n), then there will be no command presented
5. If A10/AP is High when Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be precharged.
6. In here, Don’t Care means logical value only, it doesn’t mean ’Don’t care for DC level of each signals’. DC level should be out of
WRITE MASK TRUTH TABLE
Note :
1.
2. In here, Don’t Care means logical value only, it doesn’t mean ’Don’t care for DC level of each signals’. DC level should be out of
Data Write
Data-In Mask
entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP period from
Prechagre command.
to activate bank until CK(n+BL/2+tRP).
to activate bank until CK(n+BL/2+1+tDPL+tRP). Last Data-In to Prechage delay(tDPL) which is also called Write Recovery
Time(tWR) is needed to guarantee that the last data have been completely written.
V
IHmin
Write Mask command masks burst write data with reference to LDQS/UDQS(Data Strobes) and it is not related with read data.
In case of x16 data I/O, LDM and UDM control lower byte(DQ0~7) and Upper byte(DQ8~15) respectively.
V
IHmin
Function
~ V
~ V
ILmax
ILmax
CKEn-1
H
H
CKEn
X
X
/CS, /RAS,
/CAS, /WE
X
X
DM
H
L
HY5DU281622FT(P) Series
ADD
R
A10/
AP
X
X
BA
Note
1,2
1,2
8