KSZ8041 Hynix Semiconductor, KSZ8041 Datasheet - Page 22

• Manufacturer Part Number: KSZ8041
• Manufacturer: Hynix Semiconductor

Rev. 0.04 /Jul. 2006
DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7
IDD1 : Operating current: One bank operation
1. Typical Case : VDD = 2.6V, T=25
2. Worst Case : VDD = 2.7V, T= 0
3. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are
4. Timing patterns
IDD7 : Operating current: Four bank operation
1. Typical Case : VDD = 2.6V, T=25
2. Worst Case : VDD= 2.7V, T= 0
3. Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on NOP edge are not
4. Timing patterns
changing. lout = 0mA
- DDR400(200Mhz, CL=3) : tCK = 5ns, CL = 3, BL = 4, tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge
changing once per clock cycle. lout = 0mA
- DDR400(200Mhz, CL=3) : tCK = 5ns, CL = 3, BL = 4, tRCD = 3*tCK, tRC = 11*tCK, tRAS = 8*tCK
Read : A0 N N R0 N N N P0 N N A0 N - repeat the same timing with random add
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
50% of data changing at every burst
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
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HY5DU281622FT(P) Series
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