XC9500 Xilinx Corp., XC9500 Datasheet - Page 5

• Manufacturer Part Number: XC9500
• Description: XC9500 5 V CPLD Family
• Manufacturer: Xilinx Corp.

All global control signals are available to each individual
macrocell, including clock, set/reset, and output enable sig-
nals. As shown in
originates from either of three global clocks or a product
DS063 (v5.1) September 22, 2003
Product Specification
I/O/GCK2
I/O/GCK3
I/O/GCK1
I/O/GSR
R
Figure
4, the macrocell register clock
Figure 4: Macrocell Clock and Set/Reset Capability
Product Term Set
Product Term Clock
Product Term Reset
Global Set/Reset
Global Clock 1
Global Clock 2
Global Clock 3
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term clock. Both true and complement polarities of a GCK
pin can be used within the device. A GSR input is also pro-
vided to allow user registers to be set to a user-defined
state.
XC9500 In-System Programmable CPLD Family
D/T
S
R
Macrocell
DS063_04_110501
5