MT90210 Zarlink Semiconductor, MT90210 Datasheet - Page 5

• Manufacturer Part Number: MT90210
• Description: 3072 Channels TDM to Dual Port RAM Multiple Rate Parallel Bus Access Circuit (MRPAC)
• Manufacturer: Zarlink Semiconductor

MT90210
2-148
Pin Description (continued)
75- 77,
63, 71,
78, 86,
17, 23,
60, 65,
69, 74,
88, 93,
58-59,
61-62,
72-73,
80-82,
84-85,
92, 99
41, 55
79,83,
66-68
89-90
4,16,
5,10,
Pin
64,
87,
70
91
94
98
28
A11-A12
P0-P1,
P2-P3,
A0-A1,
A2-A4,
A5-A7,
A8-A9,
Strobe
Name
P5-P7
WBC
V
V
A10,
RBC
V
V
P4,
DD2
SS2
DD
SS
Parallel Input/Output Data Bus. This 8 bit data bus is a bidirectional parallel port used to
perform 8-bit transactions between the MT90210 and the external dual port RAM. Data is
clocked in and out of the P0-P7 parallel port according to Figures 22 and 23.
Strobe Output. This output is typically connected to the Chip-enable input of the external
dual port RAM. It is kept low during all read cycles, stays high during inactive periods and
goes low for the last half of a memory write cycle.
External Memory Address Outputs A0-A12. These 13 address output lines are provided
Read Data Block Complete (output) . A transition on this output is used to notify the
external CPU that the MT90210 has finished reading the contents of one entire 125 µ s
frame from the external dual port memory (e.g.; from addresses 0000h to 0FFFh in modes
3, 4 or 5). Whenever RBC toggles, the MT90210 starts reading the next half of the memory
(addresses 1000h to 1FFFh) while the local CPU updates the first half with more data to
be sent. RBC toggles every 125 µ s. When this signal is low, the MT90210 is reading the
lower memory block.
Write Data Block Complete (Output). A transition on this output is used to notify the
external CPU that the MT90210 has finished writing the contents of one entire 125 µ s
frame into the external dual port memory (e.g; from addresses 0000h to 0FFFh in modes
3,4 or 5). Once WBC toggles, the local CPU can access the Dual port memory to get the
data while the MT90210 writes the contents of the next 125 µ s frame into the other half
(addresses 1000h to 1FFFh) of the dual port memory. WBC toggles every 125 µ s. When
this signal is low, the MT90210 is writing to the lower memory block.
Supply Input. +5V.
Supply Input. +5V.
Ground.
Ground.
by the MT90210 to allow a direct connection to an external dual port RAM.
Description