MT9041 Zarlink Semiconductor, MT9041 Datasheet
MT9041
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MT9041 Summary of contents
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... The MT9041B generates ST-BUS clock and framing signals that are phase locked to either a 2.048MHz, 1.544MHz, or 8kHz input reference. The MT9041B is compliant with AT&T TR62411 and Bellcore GR-1244-CORE Stratum 4 Enhanced, Stratum 4, and ETSI ETS 300 011. It will meet the jitter tolerance, jitter transfer, intrinsic jitter, frequency accuracy, capture range and phase change slope requirements for these specifications ...
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... Clock 4.096MHz (CMOS Output). This output is used for ST-BUS operation at 2.048Mb/s and 4.096Mb/s. MT9041B VDD 5 25 IC0 OSCo 6 24 IC0 OSCi F16o MT9041B 22 IC0 8 F0o 21 9 IC0 F8o 10 20 IC1 C1.5o IC0 Figure 2 - Pin Connections Description nominal Zarlink Semiconductor Inc ...
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... Figure functional block diagram which is described in the following sections. Frequency Select MUX Circuit The MT9041B operates on the falling edges of one of three possible input reference frequencies (8kHz, 1.544MHz or 2.048MHz). The frequency select inputs (FS1 and FS2) determine which of the three frequencies may be used at the reference input (REF) ...
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... Digital Phase Lock Loop (DPLL) The DPLL of the MT9041B consists of a Phase Detector, Limiter, Loop Filter, Digitally Controlled Oscillator, and a Control Circuit (see Figure 3). Phase Detector - the Phase Detector compares the primary reference signal (REF) with the feedback signal from the Frequency Select MUX circuit, and provides an error signal corresponding to the phase difference between the two ...
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... All frame pulse and clock outputs have limited driving capability, and should be buffered when driving high capacitance (e.g. 30pF) loads. Master Clock The MT9041B can use either a clock or crystal as the master timing source. For recommended master timing circuits, see the Applications - Master Clock section. Control and Modes of Operation The MT9041B can operate either in Normal or Freerun modes ...
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... F8o, F16o) signals, which are synchronized to reference input (REF). The input reference signal may have a nominal frequency of 8kHz, 1.544MHz or 2.048MHz. From a reset condition, the MT9041B will take seconds for the output signal to be phase locked to the reference. The reference frequencies are selected by the frequency control pins FS2 and FS1 as shown in Table 1. ...
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... Frequency Accuracy Frequency accuracy is defined as the absolute tolerance of an output clock signal when it is not locked to an external reference, but is operating in a free running mode. For the MT9041B, the Freerun accuracy is equal to the Master Clock (OSCi) accuracy. Capture Range Also referred to as pull-in range. This is the input frequency range over which the synchronizer must be able to pull into synchronization. The MT9041B capture range is equal to ± ...
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... The observation period is usually the time from the disturbance, to just after the synchronizer has settled to a steady state. In the case of the MT9041B, the output signal phase continuity is maintained to within ±5ns at the instance (over one frame) of mode changes. The total phase shift may accumulate up to ±200ns over many frames. The rate of change of the ± ...
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... Tolerance: 25ppm 0C to 70C Rise & Fall Time: 8ns (0.5V 4.5V 50pF) Duty Cycle: 45% to 55% The output clock should be connected directly (not AC coupled) to the OSCi input of the MT9041B, and the OSCo output should be left open as shown in Figure 5. MT9041B MT9041B +5V OSCi +5V 20MHz OUT ...
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... Parallel Load Capacitance: 32pF Ω Maximum Series Resistance: 35 Approximate Drive Level: 1mW e.g., CTS R1027-2BB-20.0MHZ ± ± ( 20ppm absolute, 6ppm 0C to 50C, 32pF, 25 MT9041B OSCi 20MHz 1MΩ 56pF 39pF 3-50pF OSCo 100Ω 1uH Figure 6 - Crystal Oscillator Circuit Ω Zarlink Semiconductor Inc. ...
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... RST pin during power down conditions. The reset low time is not critical but should be greater than 300ns. Power Supply Decoupling The MT9041B has two VDD (+5V) pins and two VSS (GND) pins. Power and decoupling capacitors should be included as shown in Figure 8. MT9041B ...
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... In this example 8 E1 link framers (MT9074) are connected to a common system backplane clock using the MT9041B. Each of the extracted clocks E1. mux which selects one of the eight input clocks as the reference to the MT9041B. The clock choice is made by a controller using the loss of signal pin LOS from the MT9074s to qualify potential references ...
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... Schmitt high-level input voltage 8 Schmitt low-level input voltage 9 Schmitt hysteresis voltage 10 Input leakage current 11 High-level output voltage 12 Low-level output voltage * Supply voltage and operating temperature are as per Recommended Operating Conditions. MT9041B - Voltages are with respect to ground (V SS Symbol PIN I PIN T ST ...
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... Supply voltage and operating temperature are as per Recommended Operating Conditions. * Timing for input and output signals is based on the worst Chislehurst of the combination of TTL and CMOS thresholds. * See Figure 10. ALL SIGNALS t t IRF, ORF Figure 10 - Timing Parameter Measurement Voltage Levels MT9041B Sym Min Max -0 +0 ±32ppm -32 +32 ± ...
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... F0o pulse width low 22 F8o pulse width high 23 F16o pulse width low 24 Output clock and frame pulse rise or fall time 25 Input Controls Setup Time 26 Input Controls Hold Time † See "Notes" following AC Electrical Characteristics tables. MT9041B Sym IRF t R8D t R15D t R2D ...
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... NOTES: 1. Input to output delay values are valid after a TRST or RST with no further state changes Figure 11 - Input to Output Timing (Normal Mode) F8o F0o F16o t C16WL C16o t C8W C8o t C4W C4o C2o C3o C1.5o MT9041B R15D R2D F0WL t F16S t C8W t C4W t ...
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... AC Electrical Characteristics - C2o (2.048MHz) Intrinsic Jitter Filtered Characteristics 1 Intrinsic jitter (4Hz to 100kHz filter) 2 Intrinsic jitter (10Hz to 40kHz filter) 3 Intrinsic jitter (8kHz to 40kHz filter) 4 Intrinsic jitter (10Hz to 8kHz filter) † See "Notes" following AC Electrical Characteristics tables. MT9041B Sym Min Max Units 0.0002 UIpp ...
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... Jitter attenuation for 10Hz@20UIpp input 4 Jitter attenuation for 60Hz@20UIpp input 5 Jitter attenuation for 300Hz@20UIpp input 6 Jitter attenuation for 10kHz@0.3UIpp input 7 Jitter attenuation for 100kHz@0.3UIpp input † See "Notes" following AC Electrical Characteristics tables. MT9041B Sym Min Max Units ...
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... Jitter tolerance for 20Hz input 4 Jitter tolerance for 300Hz input 5 Jitter tolerance for 400Hz input 6 Jitter tolerance for 700Hz input 7 Jitter tolerance for 2400Hz input 8 Jitter tolerance for 3600Hz input † See "Notes" following AC Electrical Characteristics tables. MT9041B Sym Min Max Units 2.9 UIpp 0.09 UIpp 1.3 UIpp 0.10 UIpp 0 ...
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... See "Notes" following AC Electrical Characteristics tables. AC Electrical Characteristics - OSCi 20MHz Master Clock Input Characteristics 1 Frequency accuracy (20 MHz nominal Duty cycle 5 Rise time 6 Fall time † See "Notes" following AC Electrical Characteristics tables. MT9041B Sym Min Max Units 150 UIpp 140 UIpp 130 UIpp 35 UIpp 25 UIpp ...
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... No filter. 33. 40Hz to 100kHz bandpass filter. 34. With respect to reference input signal frequency. 35. After a RST or TRST. 36. Master clock duty cycle 40% to 60%. MT9041B 21 Zarlink Semiconductor Inc. Data Sheet ...
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