MT9041 Zarlink Semiconductor, MT9041 Datasheet - Page 5

• Manufacturer Part Number: MT9041
• Description: Single Reference Frequency Selectable Digital PLL With Multiple Clock Outputs For T1/E1 Trunk And Backplane Synchronization
• Manufacturer: Zarlink Semiconductor

The frame pulse outputs (F0o, F8o, F16o) are generated directly from the C16 clock.
The T1 and E1 signals are generated from a common DPLL signal. Consequently, the clock outputs C1.5o, C3o,
C2o, C4o, C8o, C16o, F0o and F16o are locked to one another for all operating states, and are also locked to the
selected input reference in Normal Mode. See Figures 11 and 12.
All frame pulse and clock outputs have limited driving capability, and should be buffered when driving high
capacitance (e.g. 30pF) loads.
Master Clock
The MT9041B can use either a clock or crystal as the master timing source. For recommended master timing
circuits, see the Applications - Master Clock section.
Control and Modes of Operation
The MT9041B can operate either in Normal or Freerun modes.
As shown in Table 2, pin MS selects between NORMAL and FREERUN modes.
Figure 4 - Output Interface Circuit Block Diagram
DPLL
From
MS
0
1
Tapped
Tapped
Delay
Delay
Line
Line
Table 2 - Operating Modes
Zarlink Semiconductor Inc.
Description of Operation
MT9041B
16MHz
12MHz
FREERUN
5
NORMAL
T1 Divider
E1 Divider
C1.5o
C2o
C4o
C8o
C16o
F0o
F8o
F16o
C3o
Data Sheet