MT9041 Zarlink Semiconductor, MT9041 Datasheet - Page 4

• Manufacturer Part Number: MT9041
• Description: Single Reference Frequency Selectable Digital PLL With Multiple Clock Outputs For T1/E1 Trunk And Backplane Synchronization
• Manufacturer: Zarlink Semiconductor

MT9041B
Data Sheet
Digital Phase Lock Loop (DPLL)
The DPLL of the MT9041B consists of a Phase Detector, Limiter, Loop Filter, Digitally Controlled Oscillator, and a
Control Circuit (see Figure 3).
Phase Detector - the Phase Detector compares the primary reference signal (REF) with the feedback signal from
the Frequency Select MUX circuit, and provides an error signal corresponding to the phase difference between the
two. This error signal is passed to the Limiter circuit. The Frequency Select MUX allows the proper feedback signal
to be externally selected (e.g., 8kHz, 1.544MHz or 2.048MHz).
Limiter - the Limiter receives the error signal from the Phase Detector and ensures that the DPLL responds to all
input transient conditions with a maximum output phase slope of 5ns per 125us. This is well within the maximum
phase slope of 7.6ns per 125us or 81ns per 1.326ms specified by Bellcore GR-1244-CORE Stratum 4E.
REF Reference
DPLL Reference
Phase
Digitally
to
Detector
Limiter
Loop Filter
Controlled
Output Interface Circuit
Oscillator
Control
Feedback Signal
Circuit
from
Frequency Select MUX
Figure 3 - DPLL Block Diagram
Loop Filter - the Loop Filter is similar to a first order low pass filter with a 1.9 Hz cutoff frequency for all three
reference frequency selections (8kHz, 1.544MHz or 2.048MHz). This filter ensures that the jitter transfer
requirements in ETS 300 011 and AT&T TR62411 are met.
Control Circuit - the Control Circuit sets the mode of the DPLL. The two possible modes are Normal and Freerun.
Digitally Controlled Oscillator (DCO) - the DCO receives the limited and filtered signal from the Loop FIlter, and
based on its value, generates a corresponding digital output signal. The synchronization method of the DCO is
dependent on the state of the MT9041B.
In Normal Mode, the DCO provides an output signal which is frequency and phase locked to the selected input
reference signal.
In Freerun Mode, the DCO is free running with an accuracy equal to the accuracy of the OSCi 20MHz source.
Output Interface Circuit
The output of the DCO (DPLL) is used by the Output Interface Circuit to provide the output signals shown in Figure
4. The Output Interface Circuit uses two Tapped Delay Lines followed by a T1 Divider Circuit and an E1 Divider
Circuit to generate the required output signals.
Two tapped delay lines are used to generate a 16.384MHz and a 12.352MHz signals.
The E1 Divider Circuit uses the 16.384MHz signal to generate four clock outputs and three frame pulse outputs.
The C8o, C4o and C2o clocks are generated by simply dividing the C16o clock by two, four and eight respectively.
These outputs have a nominal 50% duty cycle.
The T1 Divider Circuit uses the 12.384MHz signal to generate two clock outputs. C1.5o and C3o are generated by
dividing the internal C12 clock by four and eight respectively. These outputs have a nominal 50% duty cycle.
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