MPC5534 Frescale, MPC5534 Datasheet - Page 11
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MPC5534
Manufacturer Part Number
MPC5534
Description
Microcontroller
Manufacturer
Frescale
Datasheet
1.MPC5534.pdf
(33 pages)
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3.8
3.9
Freescale Semiconductor
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Selectable drive strengths through pad control in SIU; 10pF, 20pF, 30pF, 50pF
21-bit address bus (2 most significant signals multiplexed with 2 chip selects)(Least significant
address bit is not supported - CAL_ADDR31)
16-bit data bus
Memory controller with support for various memory types:
— non-burst SDR Flash and SRAM
— Asynchronous/legacy Flash and SRAM
— Most standard memories used with the MPC5xx family
Bus monitor (shared with EBI)
— User selectable
— Programmable timeout period (with 8 external bus clock resolution)
Configurable wait states (via chip selects)
Three chip-select (CAL_CS[0],CAL_CS[2:3]) signals (CAL_CS[2:3] multiplexed with 2 most
significant address signals CAL_ADDR[10:11])
Two write/byte enable (WE[0:1]/BE[0:1]) signals
Configurable bus speed modes (shared with EBI)
— system frequency
— 1/2 of system frequency
— 1/4 of system frequency
Optional automatic CLKOUT gating to save power and reduce EMI
Compatible with MPC5xx external bus (with some limitations)
Selectable drive strengths; 10pF, 20pF, 30pF, 50pF
System configuration
— MCU reset configuration via external pins
— Pad configuration control
System reset monitoring and generation
— Power-on reset support
— Reset status register provides last reset source to software
— Glitch detection on reset input
— Software controlled reset assertion
External interrupt
Calibration Bus
System Integration Unit (SIU)
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MPC5534 Microcontroller Product Brief, Rev. 0.0
MPC5534 Features List
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