MPC5534 Frescale, MPC5534 Datasheet - Page 4

• Manufacturer Part Number: MPC5534
• Description: Microcontroller
• Manufacturer: Frescale

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Block Diagram
1
Figure 1
4
MPC5500 Device Module Acronyms
CAN
DSPI
DMA
eMIOS
eQADC – Enhanced queued analog/digital converter
eSCI
eTPU
FMPLL – Frequency modulated phase-locked loop
SRAM
shows a top-level block diagram of the MPC5534.
Block Diagram
– Controller area network (FlexCAN)
– Deserial/serial peripheral interface
– Enhanced direct memory access
– Enhanced modular I/O system
– Enhanced serial communications interface
– Enhanced time processing units
– Static RAM
Regulator
Interface
Control
FMPLL
Nexus
1.5V
1 Mbyte
channel
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Flash
eTPU
Peripheral Bridge A (PBRIDGE_A)
32
channels
Slave
eDMA
64
Master
2.5K Data
12K Code
System/Bus
Integration
RAM
RAM
e200z3 Core
Processing
Execution
Multiply
MPC5534 Microcontroller Product Brief, Rev. 0.0
Engine
Integer
Nexus
Signal
JTAG
Unit
Unit
Figure 1.
Slave
channel
Prediction Unit
eMIOS
64-bit General
Instruction
24
Registers
Registers
Branch
Purpose
Purpose
Memory Management Unit
Crossbar Switch (XBAR)
Special
LEGEND
Unit
MPC5534
64 Kbyte
Master
SRAM
Slave
e200z3 Core Component Acronyms
DEC
FIT
TB
WDT
Load/Store Unit
(FIT, TB, DEC)
Length Encoded
Core Timers
Exception
Instruction
Handler
Block Diagram
Variable
Unit
– Decrementer
– Fixed interval timer
– Time base
– Watchdog timer
Peripheral Bridge B (PBRIDGE_B)
Master
Slave
Interrupt Controller
Master
Slave
Interface
External
Master
Module
Assist
Boot
Freescale Semiconductor
eQADC
AMUX
ADCi
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