MPC8323E Freescale Semiconductor, MPC8323E Datasheet - Page 47

• Manufacturer Part Number: MPC8323E
• Description: Integrated Communications Processor Family Hardware Specifications
• Manufacturer: Freescale Semiconductor

Figure 41
21 Package and Pin Listings
This section details package parameters, pin assignments, and dimensions. The MPC8323E is available in
a thermally enhanced Plastic Ball Grid Array (PBGA); see
MPC8323E PBGA,”
information on the PBGA.
21.1
The package parameters are as provided in the following list. The package type is 27 mm × 27 mm, 516
PBGA.
21.2
Figure 42
package.
Freescale Semiconductor
Skew among RXP, RXN, and RXD
Notes:
1. The symbols used for timing specifications follow the pattern of t
2. Skew measurements are done at OV
and t
USB receive signals skew (RS) among RXP, RXN, and RXD (PND). Also, t
transmit signals skew (TS) between TXP and TXN (PN).
MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
(first two letters of functional block)(state)(signal)
Package outline
Interconnects
Pitch
Module height (typical)
Solder Balls
Ball diameter (typical)
Mechanical Dimensions of the MPC8323E PBGA
Package Parameters for the MPC8323E PBGA
provide the AC test load for the USB.
the mechanical dimensions and bottom surface nomenclature of the MPC8323E, 516-PBGA
Parameter
and
Output
Section 21.2, “Mechanical Dimensions of the MPC8323E PBGA,”
Table 54. USB General Timing Parameters (continued)
DD
/2 of the rising or falling edge of the signals.
Figure 41. USB AC Test Load
Symbol
for transmit signals. For example, t
t
USRPND
Z
0
= 50 Ω
1
27 mm × 27 mm
1.00 mm
2.25 mm
62 Sn/36 Pb/2 Ag (ZQ package)
95.5 Sn/0.5 Cu/4Ag (VR package)
516
0.6 mm
Min
—
(first two letters of functional block)(state)(signal)
Section 21.1, “Package Parameters for the
R
USTSPN
L
= 50 Ω
Max
100
USRSPND
symbolizes USB timing (US) for the USB
symbolizes USB timing (US) for the
OV
Unit
ns
DD
/2
Low speed transitions
Package and Pin Listings
for receive signals
Notes
for
47