MT8926AE Zarlink Semiconductor, MT8926AE Datasheet - Page 12

• Manufacturer Part Number: MT8926AE
• Description: MT8926 - T1 Performance Monitoring Adjunct Circuit (PMAC)
• Manufacturer: Zarlink Semiconductor

1.9
The PMAC has two timer outputs, 1SEC pin and CSTo TMR bit, which are derived from the 8 kHz ST-BUS frame
pulse F0i. These signals have been implemented to provide the interface controller with a timing reference for the
transmission of T1.403/408 message-oriented performance data over the FDL. See the Application section for an
explanation of T1.403/408 FDL Message Transfer.
The 1SEC output (pin 19) changes state once every half second, and therefore, has a period of one second. The
relationship between the 1SEC output and the frame pulse F0i is shown in Figure 16 on page 29.
TMR is bit one of the PMAC Miscellaneous Status Word (CSTo channel 7, see Table 5 on page 10). It changes state
once per second on the rising edge of the 1SEC output, and thus, has a two second period. Therefore, TMR will
change state 62 C2i clock cycles (or ST-BUS bit times) after the frame pulse that immediately precedes the rising
edge of the 1SEC output.
1.10
The MT8926 has two four bit counters, the Framing Error Counter (FE) and the Severely Errored Framing Event
Counter (SE). The FE counter will be incremented each time a single framing error in the T1 signal is received. The
SE counter will be incremented by the reception of a T1 framing pattern with an error rate that is greater than or
equal to two out of six bits. See Table 8 on page 13 for errored frame event counter details.
Table 6 on page 12 illustrates the Terminal Framing bits (F
framing pattern. Refer to Table 18 on page 22 for the ESF framing pattern.
Table 7 on page 12 illustrates which framing bits are included in the framing error calculations in SF and ESF modes
with the Framing Pattern Selection bit (FSel), CSTi1 channel 11 bit 3, high and low. Bits marked "1" or "0" are
counted, bits marked "X" are excluded.
When an SF signal is being received and FSel is low the counters are incremented by F
FSel must be high for the extended superframe FPS bits or both SF F
that the twelfth SF framing bit (the sixth F
alarm. The ALRM bit of the Master Status Word 1 (CSTo channel 15 bit 5) will be high if the received alternate yellow
alarm bit is high. The ALRM bit will always be low if FSel is low.
MT8926
12
Timer Outputs
Framing Error Event Counters
Table 7 - Framing Bits which Affect the SE and FE Counters
Framing Select
Frame #
FSel=0
FSel=1
Table 6 - D3/D4 or SF Frame Pattern
10
11
12
1
2
3
4
5
6
7
8
9
S
framing bit) is excluded because it can be used as an SF alternate yellow
101010
101010
SF (F
F
1
0
1
0
1
0
T
T
T )
) and Signalling Framing bits (F
XXXXXX
00111X
SF (F
T
S )
and F
F
0
0
1
1
1
0
ESF (FPS)
S
S
XXXXXX
001011
bits to be included. It should be noted
T
framing bit error events.
S
) of the SF or D3/D4
Data Sheet
SEMICMF.019