MT8926AE Zarlink Semiconductor, MT8926AE Datasheet - Page 18

• Manufacturer Part Number: MT8926AE
• Description: MT8926 - T1 Performance Monitoring Adjunct Circuit (PMAC)
• Manufacturer: Zarlink Semiconductor

In slave or loop-timed operation 8KEn of the PMAC Control Word (Table 14 on page 16, CSTi1 channel 11 bit 2)
will be high, which will pass the signal on E8Ki through to E8Ko. In Master mode or if loop-timing is acquired from
another interface, 8KEn must be low, which will make E8Ko high.
1.15
The MT8926 interrupts originate from eight sources, which are divided into two groups. Group one (G1) contains
ALRM (SF Yellow Alarm), RAI (ESF Yellow Alarm), SLIP and SYN - all except SLIP must be cleared by some means
external to the MT8926. Group two (G2) contains SEI, FSI, CSI, and BSI - these can be cleared via the MT8926.
See Table 16 on page 19 Table 17 on page 20 for further information.
The interrupting mechanism is controlled by the interrupt acknowledge bit (INTA) of the PMAC control word
(Table 14 on page 16). The status of the interrupts is output on IRQ. This will allow the three valid states described
in Table 15 on page 18.
In the Cleared state (INTA = 0) interrupt sources are ignored and IRQ will always be high impedance. If the interrupts
are not being used, then INTA should remain in the Cleared state. When the MT8926 is in the Armed state and an
interrupt occurs, it will go to the Triggered state (IRQ = 0).
When a G1 interrupt occurs and IRQ goes low (Triggered), no other G1 or G2 interrupts will affect IRQ. If IRQ is
then Cleared and re-Armed, only an active G2 interrupt can Trigger IRQ low unless the G1 interrupt has been
removed. That is, both the MT8926 interrupt mechanism and the interrupting source of a group must be cleared
before a further interrupt of that group can cause IRQ to go low. The only exception to this is SEI, which can be
MT8926
18
Delayed
Frame
Pulse**
INTERRUPT
SOURCES
From
Snap-shot
registers
MT8976/77
SLIP
MT8976/77
Delay
Interrupts
SEI*
FSI
CSI
BSI
ALRM
SYN
Detector
RAI
Toggle
Group 2
R
INTA
Group 1
Figure 8 - Functional Schematic of Interrupt Mechanism
Triggered
Cleared
Armed
State
Table 15 - Interrupt States
INTA Bit
D
D
0
1
1
*
** Delayed Frame Pulse occurs during Bit 7 of ST-BUS Channel 1.
SEI is reset to 0 when INTA = 0.
Q
Q
V
V
DD
DD
High Impedance
High Impedance
D
D
IRQ Output
R
R
Q
Q
0
D
R
Data Sheet
Q
SEMICMF.019
IRQ
.