MT8926AE Zarlink Semiconductor, MT8926AE Datasheet - Page 17

• Manufacturer Part Number: MT8926AE
• Description: MT8926 - T1 Performance Monitoring Adjunct Circuit (PMAC)
• Manufacturer: Zarlink Semiconductor

SEMICMF.019
Data Sheet
When the MT8926 is synchronized to an SF T1 signal, its receive FDL functions are disabled. BOMV of the PMAC
Miscellaneous Status Register and RAI of Master Status Word 1 will be zero.
1.14
Figure 9 on page 21 illustrates a typical MT8976/77 - MT8926 application. This diagram shows E8Ko (an 8 kHz
output aligned with the received framing bit) of the T1 framer connected to E8Ki of the PMAC. The PMAC uses this
signal for frame alignment, therefore, the 8kHSel (Master Control Word 1) of the MT8976/77 must be active for the
framer - PMAC combination to function properly, even if the interface is in master mode. See the MT8976/77 data
sheet.
Bit
0
To System
Control
MT8952
System
Control
CDSTo
CDSTi
CKi
8 kHz Control
{
FDLEn
Name
PCW FDLEn = 1 - Transmission of a Bit-oriented Message over the FDL.
PCW FDLEn = 0 - Transmission of an MT8952 (HDLC Controller) assembled message-oriented signal over the FDL.
Table 14 - C Control Word (CSTi1 Channel 11) (continued)
CSTo
1SEC
FDLi
Facility Data Link Enable. FDLEn = 1 enables transmission of the facility data link bit-
oriented messages on FDLo. The BOM byte is stored in the TxBOM register
(Table 13 on page 15, CSTi1 Channel 7). See Figure 7 on page 17 for illustration.
When FDLEn = 0, the data received on FDLi is multiplexed back out of the MT8926
on FDLo. See Figure 19 on page 30 for timing.
Figure 7 - T1.403/408 FDL Message Transmission
FDLEn
0
1
To PMAC Control
X
1
2 TO 1 MUX
MT8926
X
1
TxBOM
X
1
X
1
X
1
X
1
0
1
CSTi1
FDLo
Description
From System
Control
CSTi1
TxFDL
TxFDLCLK
RxFDL RxFDLCLK
MT8976/77
TxA
TxB
MT8926
RxA
RxB
ECLK
17