MT8926AE Zarlink Semiconductor, MT8926AE Datasheet - Page 19

• Manufacturer Part Number: MT8926AE
• Description: MT8926 - T1 Performance Monitoring Adjunct Circuit (PMAC)
• Manufacturer: Zarlink Semiconductor

SEMICMF.019
Data Sheet
cleared by INTA ( see Table 11 on page 14).
A PMAC interrupting signal is either a low-to-high transition or a change in state (SLIP), therefore, for IRQ to go low
the MT8926 must be Armed before the initiating edge occurs. In the case where all interrupts are quiescent and
then an interrupt becomes active, while the MT8926 is in its Clear state, IRQ will remain in a high impedance
condition. This is true even if the MT8926 is then put in the Armed state and the interrupt persists (see Figure 8 on
page 18).
It should be noted that when an SF mode T1 signal is being received the MT8926 CRC error counter will be
incremented once every two superframes (24 frames or 3 msec.). This is because SF mode T1 has no CRC bits.
Therefore, the CRC circuitry of the MT8976/77 will compare the calculated CRC remainder with the received FS
bits, which will result in a mismatch. This will increment the MT8976/77 and MT8926 CRC error counters.
The MT8926 CRC error counter will count to 255 and then overflow to zero, which will cause an interrupt (IRQ).
Therefore, when an SF mode T1 signal is being received an interrupt will be asserted every 256 X 3 msec. = 768
msec. This can be avoided by clearing the CRC error counter before it overflows. A change of state of the 1SEC
output (once every 0.5 seconds) can be used to trigger a high-to-low transition of the CRCR bit (CSTi1 channel 11
bit 5, PMAC Control Word). This will ensure the CRC error counter never overflows.
1.16
The MT8976 SLIP and SYN status bits are passed to the PMAC via the MT8976/77 CSTo to PMAC CSTi0
connection. A MT8926 interrupt will be initiated when the SLIP bit of the framer changes state. This is the only
interrupt source that does not have to be cleared before another interrupt of that group can make IRQ go low.
Therefore, when IRQ is returned to a high impedance condition after a SLIP interrupt and all other G1 interrupts are
quiescent, any G1 interrupt can make IRQ to go low.
A Low-to-High transition of the MT8976/77 SYN bit will initiate a PMAC interrupt. This loss of synchronization
situation may indicate that a loss of signal condition (LOS) exists or that an all ones (AIS or Blue Alarm) is being
received. Therefore, the SYN interrupt service routine should check the state of the AIS and LOS bits of CSTo.
‡ G1 interrupts are cleared when SYN, ALRM, and RAI = 0.
† The SYN interrupt indicates that a LOS or a AIS condition may exist.
Note: AND denotes a logical and.
Signal
ALRM
SYN
SLIP
RAI
†
‡
SLIP and SYN Interrupts
ALRM bit low to high AND other G1 interrupts
quiescent AND IRQ high impedance.
RAI bit low to high AND other G1 interrupts
quiescent and IRQ high impedance.
CSTi0/CSTo Channel 15 Bit 1 (SLIP) changes state
AND other G1 interrupts quiescent AND IRQ high
impedance.
CSTi0/CSTo Channel 15 Bit 0 (SYN) low to high
AND other G1 interrupts inactive AND IRQ high
impedance.
Table 16 - Group One (G1) Interrupt Activation and Clearing
To Trigger interrupt (IRQ low)
The INTA bit of the PMAC Control Word
(CSTi1 channel 11 bit 1) should be made
low to clear the interrupt mechanism (IRQ
high impedance). All G1 interrupts must be
quiescent and then INTA must be made
high before a further interrupt can be
generated from G1.
See MT8976/77 data sheet master status
word 1 for information on the SLIP and
SYN bits.
To Clear and Arm interrupt
impedance)
MT8926
(
IRQ high
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