MD3331-D64-V3 M-Systems Inc., MD3331-D64-V3 Datasheet - Page 48

• Manufacturer Part Number: MD3331-D64-V3
• Description: Diskonchip Millennium Plus
• Manufacturer: M-Systems Inc.

DiskOnChip Millennium Plus derives its internal clock signal from the CE#, OE# and WE# inputs. Since access to
DiskOnChip Millennium Plus’ registers is volatile, much like a FIFO or UART, ensure that these signals have clean
rising and falling edges, and are free from ringing that can be interpreted as multiple edges. PC board traces for
these three signals must either be kept short or properly terminated to guarantee proper operation.
When designing a 16-bit platform for both 8-bit and 16-bit DiskOnChip TSOP-I devices, please refer to application
note AP-DOC-054, Connecting DiskOnChip TSOP-I to a 16-Bit Platform.
9.3.2 Multiplexed Interface
DiskOnChip Millennium Plus 16MB can also be configured to work with a multiplexed interface where data and
address line are multiplexed. In this configuration, AVD# input is driven by the host's AVD# signal, and the D[15:0]
pins, used for both address and data, are connected to the host AD[15:0] bus. DiskOnChip address lines A[12:0] and
BHE# should be connected to VSS. IF_CFG should be connected to VCC.
Note: When the device operates with a multiplexed interface, the value of ID1 is internally forced to logic 0 due to
This mode is automatically entered when a falling edge is detected on AVD# input. This edge must occur after
RSTIN# is negated and before OE# and CE# are both asserted, i.e. the first read cycle made to DiskOnChip must
observe the multiplex mode protocol.
Please refer to Section 2.3 for pinout and signal descriptions and to Section 10.4.3 for timing specifications for a
multiplexed interface.
9.4
9.4.1 Hardware Configuration
To configure the hardware, connect the IRQ# pin to the host interrupt input.
Note: A nominal 10 KΩ pull-up resistor must be connected to this pin.
9.4.2 Software Configuration
Configuring the software to support the IRQ# interrupt is performed in two stages.
Stage 1
Configure the software so that upon system initialization, the following steps occur:
1. The correct value is written to the Interrupt Control register to configure DiskOnChip for:
2. The host interrupt is configured to the selected input sensitivity, either edge or level.
3. The handshake mechanism between the interrupt handler and the OS is initialized.
4. The interrupt service routine to the host interrupt is connected and enabled.
Stage 2
Configure the software so that for every long flash I/O operation, the following steps occur:
1. The correct value is written to the Interrupt Control register to enable the IRQ# interrupt.
2. The flash I/O operation starts.
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Note: Refer to Section 7.10 for further information on the value to be written to this register.
Note: Refer to Section 7.10 for further information on the value to be written to this register.
the host AVD# signal. Since the only possible ID0 values are 0 and 1, a cascaded configuration supports up
to two devices instead of four as with a standard interface.
Implementing the Interrupt Mechanism
Interrupt source: Flash ready and/or data protection
Output sensitivity: Either edge or level triggered
Data Sheet, Rev. 1.7
DiskOnChip Millennium Plus 16/32/64MByte
93-SR-002-03-8L