MD3331-D64-V3 M-Systems Inc., MD3331-D64-V3 Datasheet - Page 67

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MD3331-D64-V3

Manufacturer Part Number
MD3331-D64-V3
Description
Diskonchip Millennium Plus
Manufacturer
M-Systems Inc.
Datasheet

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10.4.6 Interrupt Timing
The interrupt timing is illustrated in Figure 29, and described in Table 24.
67
IRQ#
1. Specified from the final positive crossing of Vcc above 2.7V.
2. If the assertion of RSTIN# occurs during a flash erase cycle, this time could be extended by up to 500 µS.
3. Normal read/write cycle timing applies. This parameter applies only when the cycle is extended until the negation of the BUSY#
signal.
4. Applies to multiplexed interface only.
T
Tw(IRQ)
Symbol
Tp (VCC-BUSY0)
Tho(RSTIN-AVD)
REC
T
T
HO
SU
T
T
T
P
W
P
(VCC-RSTIN)
Symbol
(BUSY-CE)
(D-BUSY1)
(BUSY1)
(BUSY0)
(RSTIN)
2
3
3
1
4
IRQ# asserted pulse width (edge mode)
1
Figure 29: IRQ# Pulse Width in Edge Mode
Table 23: Power-Up Timing Parameters
VCC/VCCQ stable to RSTIN#
VCC/VCCQ stable to BUSY#
RSTIN# asserted pulse width
RSTIN#
RSTIN#
RSTIN#
Data valid to BUSY#
BUSY#
Table 24: Interrupt Timing
Description
Data Sheet, Rev. 1.7
Description
to AVD# low hold
to BUSY#
to BUSY#
to CE#
Tw(IRQ)
Min
500
30
70
0
0
DiskOnChip Millennium Plus 16/32/64MByte
Min
300
Max
500
1.3
50
Max
800
Units
ms
µs
µs
ns
ns
ns
ns
ns
Units
nS
93-SR-002-03-8L

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