TS68040 ATMEL Corporation, TS68040 Datasheet - Page 3

• Manufacturer Part Number: TS68040
• Description: 32-bit Mpu, 25-33 MHZ
• Manufacturer: ATMEL Corporation

TS 68040
A - GENERAL DESCRIPTION
Figure 1 : Block diagram.
1 - INTRODUCTION
The TS 68040 is an enhanced, 32-bit, HCMOS microprocessor that combines the integer unit processing capabilities of the
TS 68030 microprocessor with independent 4K-byte data and instruction caches and an on-chip FPU. The TS 68040 maintains
the 32-bit registers available with the entire TS 68000 Family as well as the 32-bit address and data paths, rich instruction
set, and versatile addressing modes. Instruction execution proceeds in parallel with accesses to the internal caches, MMU
operations, and bus controller activity. Additionally, the integer unit is optimized for high-level language environments.
The TS 68040 FPU is user-object-code compatible with the TS 68882 floating-point coprocessor and conforms to the
ANSI / IEEE Standard 754 for binary floating-point arithmetic. The FPU has been optimized to execute the most commonly
used subset of the TS 68882 instruction set, and includes additional instruction formats for single and double-precision
rounding of results. Floating-point instructions in the FPU execute concurrently with integer instructions in the integer unit.
The MMUs support multiprocessing, virtual memory systems by translating logical addresses to physical addresses using
translation tables stored in memory. The MMUs store recently used address mappings in two separate ATCs-on-chip. When
an ATC contains the physical address for a bus cycle requested by the processor, a translation table search is avoided and
the physical address is supplied immediately, incurring no delay for adress translation. Each MMU has two transparent
translation registers available that define a one-to-one mapping for adress space segments ranging in size from 16 Mbytes
to 4 Gbytes each.
Each MMU provides read-only and supervisor-only protections on a page basis. Also, processes can be given isolated
address spaces by assigning each a unique table structure and updating the root pointer upon a task swap. Isolated address
spaces protect the integrity of independent processes.
The instruction and data caches operate independently from the rest of the machine, storing information for fast access by
the execution units. Each cache resides on its own internal address bus and internal data bus, allowing simultaneous access
to both. The data cache provides writethrough or copyback write modes that can be configured on a page-by-page basis.
The TS 68040 bus controller supports a high-speed, nonmultiplexed, synchronous external bus interface, which allows the
following transfer sizes : byte, word (2 bytes), long word (4 bytes), and line (16 bytes). Line accesses are performed using
burst transfers for both reads and writes to provide high data transfer rates.
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